hdlcoder.WorkflowConfig class

Package: hdlcoder

Configure HDL code generation and deployment workflows

Description

Use the hdlcoder.WorkflowConfig object to set HDL workflow options for the hdlcoder.runWorkflow function. You can customize the hdlcoder.WorkflowConfig object for these workflows:

Generic ASIC/FPGA
FPGA-in-the-Loop (requires HDL Verifier™)
FPGA Turnkey
IP Core Generation
Simulink Real-Time FPGA I/O (requires Simulink^® Real-Time™)

A best practice is to use the HDL Workflow Advisor to configure the workflow, and then export a workflow script. The commands in the workflow script create and configure the hdlcoder.WorkflowConfig object. See Run HDL Workflow with a Script.

Construction

hdlcoder.WorkflowConfig(Name,Value) creates a workflow configuration object for you to specify your HDL code generation and deployment workflows, with additional options specified by one or more Name,Value pair arguments.

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

`SynthesisTool` — Synthesis tool name
`'Xilinx Vivado'` (default) | `'Altera QUARTUS II'` | `'Xilinx ISE'`

Name of the synthesis tool, specified as a character vector.

Example: 'SynthesisTool','Altera QUARTUS II' creates a workflow configuration object with 'Altera QUARTUS II' as the synthesis tool and 'Generic ASIC/FPGA' as the target workflow.

`TargetWorkflow` — Specify the target workflow
`'Generic ASIC/FPGA'` (default) | `'FPGA Turnkey'` | `'IP Core Generation'` | `'FPGA-in-the-Loop'` | `'Simulink Real-Time FPGA I/O'`

Target workflow for HDL code generation, specified as a character vector.

Example: 'TargetWorkflow','IP Core Generation' creates a workflow configuration object with 'Xilinx Vivado' as the synthesis tool and 'IP Core Generation' as the target workflow.

Properties

expand all

Generic ASIC/FPGA Workflow

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

High-level synthesis tool objective, specified as one of these values.

`hdlcoder.Objective.None` (default)	Do not generate additional Tcl commands.
`hdlcoder.Objective.SpeedOptimized`	Generate synthesis tool Tcl commands to optimize for speed.
`hdlcoder.Objective.AreaOptimized`	Generate synthesis tool Tcl commands to optimize for area.
`hdlcoder.Objective.CompileOptimized`	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is Xilinx^® ISE and your target workflow is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

`RunTaskGenerateRTLCodeAndTestbench` — Enable task to generate code and test bench
`true` (default) | `false`

Enable or disable workflow task to generate code and test bench, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`RunTaskVerifyWithHDLCosimulation` — Enable task to verify generated code with HDL cosimulation
`true` (default) | `false`

Enable or disable task to verify the generated code with HDL cosimulation, specified as a logical. This option takes effect only when GenerateCosimulationModel is true.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Verify with HDL Cosimulation task.

`RunTaskCreateProject` — Enable task to create synthesis tool project
`true` (default) | `false`

Enable or disable task to create a synthesis tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

Enable or disable task to launch the synthesis tool and run logic synthesis, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera^® Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

Enable or disable task to map the synthesized logic to the target device, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`

Enable or disable task to run the place and route process, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.

`RunTaskRunSynthesis` — Enable task to launch Xilinx Vivado^® and run synthesis
`true` (default) | `false`

Enable or disable task to launch Xilinx Vivado and run synthesis, specified as a logical. This task is available only when your synthesis tool is Xilinx Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Synthesis task.

`RunTaskRunImplementation` — Enable task to launch Xilinx Vivado and run implementation
`true` (default) | `false`

Enable or disable task to launch Xilinx Vivado and run the implementation step, specified as a logical. This task is available only when your synthesis tool is Xilinx Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Implementation task.

`RunTaskAnnotateModelWithSynthesisResult` — Enable task to analyze timing information and highlight critical paths
`true` (default) | `false`

Enable or disable task to analyze pre- or post-routing timing information and highlight critical paths in your model, specified as a logical. This task is available only when the target workflow is Generic ASIC/FPGA.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

`GenerateRTLCode` — Generate HDL code
`true` (default) | `false`

Option to generate HDL code in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`GenerateTestbench` — Generate HDL test bench
`false` (default) | `true`

Option to generate an HDL test bench in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`GenerateValidationModel` — Generate validation model
`false` (default) | `true`

Generate a validation model, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`AdditionalProjectCreationTclFiles` — Additional project creation Tcl files to include in your synthesis project
`''` (default) | character vector

Additional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

Example: 'L:\file1.tcl;L:\file2.tcl;'

`SkipPreRouteTimingAnalysis` — Skip pre-route timing analysis `logical`
`false` (default) | `true`

Skip pre-route timing analysis, specified as a logical. If your tool does not support early timing estimation, set to true.

When you enable this option, CriticalPathSource is set to 'post-route'

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`IgnorePlaceAndRouteErrors` — Ignore place and route errors
`false` (default) | `true`

Ignore place and route errors, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.

`CriticalPathSource` — Critical path source
`'pre-route'` (default) | `'post-route'`

Critical path source, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`CriticalPathNumber` — Number of critical paths to annotate
1 (default) | 2 | 3

Number of critical paths to annotate, specified as a positive integer from 1 to 3.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

`ShowAllPaths` — Show all critical paths
`false` (default) | `true`

Show all critical paths, including duplicate paths, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

`ShowDelayData` — Annotate cumulative timing delay on each critical path
`true` (default) | `false`

Annotate the cumulative timing delay on each critical path, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

`ShowUniquePaths` — Show only the first instance of a critical path
`false` (default) | `true`

Show only the first instance of a critical path that is duplicated, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

`ShowEndsOnly` — Show only endpoints of each critical path
`false` (default) | `true`

Show the endpoints of each critical path, omitting connecting signal lines, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

FPGA-in-the-Loop

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

`RunTaskGenerateRTLCodeAndTestbench` — Enable task to generate code and test bench
`true` (default) | `false`

Enable or disable workflow task to generate code and test bench, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`RunTaskVerifyWithHDLCosimulation` — Enable task to verify generated code with HDL cosimulation
`true` (default) | `false`

Enable or disable task to verify the generated code with HDL cosimulation, specified as a logical. This option takes effect only when GenerateCosimulationModel is true.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Verify with HDL Cosimulation task.

`RunTaskBuildFPGAInTheLoop` — Enable task to generate a model that contains a FIL block and a testbench around the FIL block
`true` (default) | `false`

Enable or disable task to generate a model that contains a FIL block and a testbench around the FIL block specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Build FPGA-in-the-Loop task.

`GenerateRTLCode` — Generate HDL code
`true` (default) | `false`

Option to generate HDL code in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`GenerateTestbench` — Generate HDL test bench
`false` (default) | `true`

Option to generate an HDL test bench in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`GenerateValidationModel` — Generate validation model
`false` (default) | `true`

Generate a validation model, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

`IPAddress` — IP address of FPGA board
`'192.168.0.2'` (default) | character vector

IP address of the FPGA board, specified as a character vector. Default address is '192.168.0.2'.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

`MACAddress` — MAC address of FPGA board
`'00-0A-35-02-21-8A'` (default) | character vector

MAC address of the FPGA board, specified as a character vector, for example '00-0A-35-02-21-8A'. In most cases, you do not have to change the Board MAC address. If you want to connect more than one FPGA board to a single computer, specify a unique MAC address for each additional board.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

`SourceFiles` — Additional HDL source files for verification
`''` (default) | character vector

Additional source files for the HDL design that you want to verify on the FPGA board, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

`Connection` — JTAG or Ethernet connection
`'JTAG'` (default) | `'Ethernet'`

Ethernet or JTAG connection type to the FPGA development board, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

`RunExternalBuild` — Run build process externally
`true` (default) | `false`

Option to run build process in parallel with MATLAB^®, specified as a logical. If this option is disabled, you cannot use MATLAB until the build is finished.

FPGA Turnkey Workflow

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

High-level synthesis tool objective, specified as one of these values.

`hdlcoder.Objective.None` (default)	Do not generate additional Tcl commands.
`hdlcoder.Objective.SpeedOptimized`	Generate synthesis tool Tcl commands to optimize for speed.
`hdlcoder.Objective.AreaOptimized`	Generate synthesis tool Tcl commands to optimize for area.
`hdlcoder.Objective.CompileOptimized`	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is Xilinx ISE and your target workflow is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

`RunTaskGenerateRTLCode` — Enable task to generate RTL code and HDL top-level wrapper
`true` (default) | `false`

Enable or disable workflow task to generate RTL code and an HDL top-level wrapper, specified as a logical. When enabled, this task also generates a constraint file that contains pin mapping information and clock constraints.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code task.

`RunTaskCreateProject` — Enable task to create synthesis tool project
`true` (default) | `false`

Enable or disable task to create a synthesis tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

Enable or disable task to launch the synthesis tool and run logic synthesis, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

Enable or disable task to map the synthesized logic to the target device, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`

Enable or disable task to run the place and route process, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.

`RunTaskRunSynthesis` — Enable task to launch Xilinx Vivado and run synthesis
`true` (default) | `false`

Enable or disable task to launch Xilinx Vivado and run synthesis, specified as a logical. This task is available only when your synthesis tool is Xilinx Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Synthesis task.

`RunTaskRunImplementation` — Enable task to launch Xilinx Vivado and run implementation
`true` (default) | `false`

Enable or disable task to launch Xilinx Vivado and run the implementation step, specified as a logical. This task is available only when your synthesis tool is Xilinx Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Implementation task.

`RunTaskGenerateProgrammingFile` — Enable task to generate FPGA programming file
`true` (default) | `false`

Enable or disable task to generate an FPGA programming file, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Programming File task.

`RunTaskProgramTargetDevice` — Enable task to program target device
`true` (default) | `false`

Enable or disable task to download the FPGA programming file to the target device, specified as a logical. This task is available only when the target workflow is FPGA Turnkey.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Program Target Device task.

`AdditionalProjectCreationTclFiles` — Additional project creation Tcl files to include in your synthesis project
`''` (default) | character vector

Additional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

Example: 'L:\file1.tcl;L:\file2.tcl;'

`SkipPreRouteTimingAnalysis` — Skip pre-route timing analysis `logical`
`false` (default) | `true`

Skip pre-route timing analysis, specified as a logical. If your tool does not support early timing estimation, set to true.

When this option is enabled, CriticalPathSource is set to 'post-route'

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`IgnorePlaceAndRouteErrors` — Ignore place and route errors
`false` (default) | `true`

Ignore place and route errors, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.

IP Core Generation Workflow

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

`ReferenceDesignToolVersion` — Current reference design tool version
character vector

Current reference design tool version, specified as a character vector, for example '2017.4'. By default, the code generator selects a reference design tool version that is compatible with the current supported tool version. It is change this default reference design tool version, HDL Coder™ generates an error.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

`IgnoreToolVersionMismatch` — Ignore mismatch in reference design tool version
`false` (default) | `true`

Whether you want the code generator to ignore a mismatch between the reference design tool version and the supported tool version, specified as a logical.By default, if there is a tool version mismatch, HDL Coder generates an error. If you set this option to true, HDL Coder generates a warning instead.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

`RunTaskGenerateRTLCodeAndIPCore` — Enable task to generate code and IP core
`true` (default) | `false`

Enable or disable workflow task to generate code and IP core for embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and IP Core task.

`RunTaskCreateProject` — Enable task to create embedded system tool project
`true` (default) | `false`

Enable or disable workflow task to create an embedded system tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Create Project task.

`RunTaskGenerateSoftwareInterface` — Enable task to generate software interface
`true` (default) | `false`

Enable or disable workflow task to generate a software interface model or script or both with IP core driver blocks for embedded C code generation, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Generate Software Interface Model task.

`GenerateSoftwareInterfaceModel` — Generate software interface model
`true` (default) | `false`

Specify whether to generate a software interface model with IP core driver blocks for embedded C code generation, specified as a logical. RunTaskGenerateSoftwareInterface must be set to true.

`GenerateSoftwareInterfaceScript` — Generate software interface script
`true` (default) | `false`

Specify whether to generate a software interface script with IP core driver blocks to test the HDL IP core functionality, specified as a logical. RunTaskGenerateSoftwareInterface must be set to true.

`RunTaskBuildFPGABitstream` — Enable task to generate bitstream for embedded system
`true` (default) | `false`

Enable or disable workflow task to generate a bitstream for the embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Build FPGA Bitstream task.

`RunTaskProgramTargetDevice` — Enable task to program connected target device
`false` (default) | `true`

Enable or disable workflow task to program the connected target device, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Program Target Device task.

`IPCoreRepository` — IP core repository folder path
`''` (default) | character vector

Full path to an IP core repository folder, specified as a character vector. The coder copies the generated IP core into the IP repository folder.

Example: 'L:\sandbox\work\IPfolder'

`GenerateIPCoreReport` — Generate HTML documentation for the IP core
`true` (default) | `false`

Option to generate HTML documentation for the IP core, specified as a logical. For details, see Custom IP Core Report.

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

High-level synthesis tool objective, specified as one of these values.

`hdlcoder.Objective.None` (default)	Do not generate additional Tcl commands.
`hdlcoder.Objective.SpeedOptimized`	Generate synthesis tool Tcl commands to optimize for speed.
`hdlcoder.Objective.AreaOptimized`	Generate synthesis tool Tcl commands to optimize for area.
`hdlcoder.Objective.CompileOptimized`	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is Xilinx ISE and your target workflow is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

`EnableIPCaching` — Create IP cache to reduce reference design synthesis time
`false` (default) | `true`

Enable or disable IP caching, specified as a logical. When you enable IP caching, the code generator creates an IP cache. The IP Core Generation workflow uses an out-of-context (OOC) workflow. This workflow synthesizes the IP in the reference design out of context from the top-level design. You can reuse this cache in subsequent project runs, which reduces reference design synthesis time. To learn more, see IP Caching for Faster Reference Design Synthesis.

In the HDL Workflow Advisor, you can specify this setting in the Create Project task.

`OperatingSystem` — Operating system
`''` (default) | character vector

Operating system for embedded processor, specified as a character vector. The operating system is board-specific.

`AddLinuxDeviceDriver` — Add IP core device driver
`false` (default) | `true`

Option to insert the IP core node into the operating system device tree on the SD card on your board, specified as a logical. This option also restarts the operating system and adds the IP core driver as a loadable kernel module.

To use this option, your board must be connected.

`RunExternalBuild` — Run build process externally
`true` (default) | `false`

Option to run build process in parallel with MATLAB, specified as a logical. If this option is disabled, you cannot use MATLAB until the build is finished.

`ReportTimingFailure` — Report timing failures as warnings or errors
`hdlcoder.ReportTimingFailure.Error` (default) | `hdlcoder.ReportTimingFailure.Warning`

Select whether to report timing failures when generating the FPGA bitstream, specified as one of these values:

`hdlcoder.ReportTimingFailure.Error` (default)	Report timing failures as errors by default.
`hdlcoder.ReportTimingFailure.Warning`	Report timing failures as errors instead of warnings. Use this option if you have implemented the custom logic to resolve timing violations in your design.

`TclFileForSynthesisBuild` — Use custom or default synthesis tool build script
`hdlcoder.BuildOption.Default` (default) | `hdlcoder.BuildOption.Custom`

Select whether to use a custom or default synthesis tool build script, specified as one of these values:

`hdlcoder.BuildOption.Default` (default)	Use the default build script.
`hdlcoder.BuildOption.Custom`	Use a custom build script instead of the default build script.

`CustomBuildTclFile` — Custom synthesis tool build script file
`''` (default) | character vector

Full path to a custom synthesis tool build Tcl script file, specified as a character vector. The contents of your custom Tcl file are inserted between the Tcl commands that open and close the project. If TclFileForSynthesisBuild is set to hdlcoder.BuildOption.Custom, you must specify a file.

If you want to generate a bitstream, the bitstream generation Tcl command must refer to the top file wrapper name and location either directly or implicitly. For example, this Xilinx Vivado Tcl command generates a bitstream and implicitly refers to the top file name and location:

launch_runs impl_1 -to_step write_bitstream

Example: 'C:\Temp\work\build.tcl'

Simulink Real-Time FPGA I/O

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

`ReferenceDesignToolVersion` — Current reference design tool version
character vector

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

`IgnoreToolVersionMismatch` — Ignore mismatch in reference design tool version
`false` (default) | `true`

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

`RunTaskGenerateRTLCodeAndIPCore` — Enable task to generate code and IP core
`true` (default) | `false`

Enable or disable workflow task to generate code and IP core for embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and IP Core task.

`RunTaskGenerateRTLCode` — Enable task to generate RTL code and HDL top-level wrapper
`true` (default) | `false`

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code task.

`RunTaskCreateProject` — Enable task to create embedded system tool project
`true` (default) | `false`

Enable or disable workflow task to create an embedded system tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Create Project task.

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

Enable or disable task to launch the synthesis tool and run logic synthesis, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

Enable or disable task to map the synthesized logic to the target device, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`

Enable or disable task to run the place and route process, specified as a logical. This task is available only when your synthesis tool is Xilinx ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.

`RunTaskGenerateProgrammingFile` — Enable task to generate FPGA programming file
`true` (default) | `false`

Enable or disable task to generate an FPGA programming file, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Programming File task.

`RunTaskGenerateSimulinkRealTimeInterface` — Enable task to generate a model that contains an interface subsystem that you can plug into a Simulink Real-Time model
`true` (default) | `false`

Enable or disable task to generate a Simulink Real-Time model that contains an interface subsystem, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Simulink Real-Time Interface task.

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

High-level synthesis tool objective, specified as one of these values.

`hdlcoder.Objective.None` (default)	Do not generate additional Tcl commands.
`hdlcoder.Objective.SpeedOptimized`	Generate synthesis tool Tcl commands to optimize for speed.
`hdlcoder.Objective.AreaOptimized`	Generate synthesis tool Tcl commands to optimize for area.
`hdlcoder.Objective.CompileOptimized`	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is Xilinx ISE and your target workflow is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

`AdditionalProjectCreationTclFiles` — Additional project creation Tcl files to include in your synthesis project
`''` (default) | character vector

Additional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

Example: 'L:\file1.tcl;L:\file2.tcl;'

`SkipPreRouteTimingAnalysis` — Skip pre-route timing analysis `logical`
`false` (default) | `true`

Skip pre-route timing analysis, specified as a logical. If your tool does not support early timing estimation, set to true.

When you enable this option, CriticalPathSource is set to 'post-route'

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

`IgnorePlaceAndRouteErrors` — Ignore place and route errors
`false` (default) | `true`

Ignore place and route errors, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.

`RunTaskBuildFPGABitstream` — Enable task to generate bitstream for embedded system
`true` (default) | `false`

Enable or disable workflow task to generate a bitstream for the embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Build FPGA Bitstream task.

`ReportTimingFailure` — Report timing failures as warnings or errors
`hdlcoder.ReportTimingFailure.Error` (default) | `hdlcoder.ReportTimingFailure.Warning`

Select whether to report timing failures when generating the FPGA bitstream, specified as one of these values:

`hdlcoder.ReportTimingFailure.Error` (default)	Report timing failures as errors by default.
`hdlcoder.ReportTimingFailure.Warning`	Report timing failures as errors instead of warnings. Use this option if you have implemented the custom logic to resolve timing violations in your design.

Methods

clearAllTasks	Disable all tasks in workflow
export	Generate MATLAB script that recreates the workflow configuration
setAllTasks	Enable all tasks in workflow
validate	Check property values in HDL Workflow CLI configuration object

Examples

collapse all

Configure and Run Generic ASIC/FPGA Workflow with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a generic ASIC/FPGA workflow script that targets a Xilinx Virtex^® 7 device and uses the Xilinx Vivado synthesis tool.

Open and view your exported HDL workflow script.

% Export Workflow Configuration Script
% Generated with MATLAB 9.5 (R2018b Prerelease) at 14:42:37 on 29/03/2018
% This script was generated using the following parameter values:
%     Filename  : 'S:\generic_workflow_example.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'sfir_fixed/symmetric_fir'
% To view changes after modifying the workflow, run the following command:
% >> hWC.export('DUT','sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system('sfir_fixed');

%% Restore the Model to default HDL parameters
%hdlrestoreparams('sfir_fixed/symmetric_fir');

%% Model HDL Parameters
%% Set Model 'sfir_fixed' HDL parameters
hdlset_param('sfir_fixed', 'GenerateCoSimModel', 'ModelSim');
hdlset_param('sfir_fixed', 'GenerateHDLTestBench', 'off');
hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7vx485t');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'ffg1761');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-2');
hdlset_param('sfir_fixed', 'TargetDirectory', 'hdl_prj\hdlsrc');


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','Generic ASIC/FPGA');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.RunTaskVerifyWithHDLCosimulation = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskRunSynthesis = true;
hWC.RunTaskRunImplementation = false;
hWC.RunTaskAnnotateModelWithSynthesisResult = true;

% Set properties related to 'RunTaskGenerateRTLCodeAndTestbench' Task
hWC.GenerateRTLCode = true;
hWC.GenerateTestbench = false;
hWC.GenerateValidationModel = false;

% Set properties related to 'RunTaskCreateProject' Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';

% Set properties related to 'RunTaskRunSynthesis' Task
hWC.SkipPreRouteTimingAnalysis = false;

% Set properties related to 'RunTaskRunImplementation' Task
hWC.IgnorePlaceAndRouteErrors = false;

% Set properties related to 'RunTaskAnnotateModelWithSynthesisResult' Task
hWC.CriticalPathSource = 'pre-route';
hWC.CriticalPathNumber =  1;
hWC.ShowAllPaths = false;
hWC.ShowDelayData = true;
hWC.ShowUniquePaths = false;
hWC.ShowEndsOnly = false;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('sfir_fixed/symmetric_fir', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is generic_workflow_example.m, at the command line, enter:

generic_workflow_example.m

Configure and Run FPGA-in-the-Loop with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is an FPGA-in-the-Loop workflow script that targets a Xilinx Virtex 5 development board and uses the Xilinx ISE synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB 9.5 (R2018b Prerelease) at 15:11:23 on 04/05/2018
% This script was generated using the following parameter values:
%     Filename  : 'C:\Users\ggnanase\Desktop\R2018b\18b_models\ipcore_timing_failure\hdlworkflow_FIL.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'sfir_fixed/symmetric_fir'
% To view changes after modifying the workflow, run the following command:
% >> hWC.export('DUT','sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system('sfir_fixed');

%% Restore the Model to default HDL parameters
%hdlrestoreparams('sfir_fixed/symmetric_fir');

%% Model HDL Parameters
%% Set Model 'sfir_fixed' HDL parameters
hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Kintex7');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7k325t');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'ffg900');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-2');
hdlset_param('sfir_fixed', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('sfir_fixed', 'TargetFrequency', 25);
hdlset_param('sfir_fixed', 'TargetPlatform', 'Xilinx Kintex-7 KC705 development board');
hdlset_param('sfir_fixed', 'Workflow', 'FPGA-in-the-Loop');


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','FPGA-in-the-Loop');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.RunTaskVerifyWithHDLCosimulation = false;
hWC.RunTaskBuildFPGAInTheLoop = true;

% Set properties related to 'RunTaskGenerateRTLCodeAndTestbench' Task
hWC.GenerateRTLCode = true;
hWC.GenerateTestbench = false;
hWC.GenerateValidationModel = false;

% Set properties related to 'RunTaskBuildFPGAInTheLoop' Task
hWC.IPAddress = '192.168.0.2';
hWC.MACAddress = '00-0A-35-02-21-8A';
hWC.SourceFiles = '';
hWC.Connection = 'Ethernet';
hWC.RunExternalBuild = true;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('sfir_fixed/symmetric_fir', hWC);
hdlcoder.runWorkflow('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is FIL_workflow_example.m, at the command line, enter:

fil_workflow_example.m

Configure and Run FPGA Turnkey Workflow with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is an FPGA Turnkey workflow script that targets a Xilinx Virtex 5 development board and uses the Xilinx ISE synthesis tool.

Open and view your exported HDL workflow script.

% Export Workflow Configuration Script
% Generated with MATLAB 8.6 (R2015b) at 14:24:32 on 08/07/2015
% Parameter Values:
%     Filename  : 'S:\turnkey_workflow_example.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA'

%% Load the Model
load_system('hdlcoderUARTServoControllerExample');

%% Model HDL Parameters
% Set Model HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'HDLSubsystem', 'hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'SynthesisTool', 'Xilinx ISE');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'SynthesisToolChipFamily', 'Virtex5');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'SynthesisToolDeviceName', 'xc5vsx50t');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'SynthesisToolPackageName', 'ff1136');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'SynthesisToolSpeedValue', '-1');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoderUARTServoControllerExample', ...
    'TargetPlatform', 'Xilinx Virtex-5 ML506 development board');
hdlset_param('hdlcoderUARTServoControllerExample', 'Workflow', 'FPGA Turnkey');

% Set Inport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_rxd', ...
    'IOInterface', 'RS-232 Serial Port Rx');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_rxd', ...
    'IOInterfaceMapping', '[0]');

% Set Outport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_txd', ...
    'IOInterface', 'RS-232 Serial Port Tx');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_txd', ...
    'IOInterfaceMapping', '[0]');

% Set Outport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/version', ...
    'IOInterface', 'LEDs General Purpose [0:7]');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/version', ...
    'IOInterfaceMapping', '[0:3]');

% Set Outport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/pwm_output', ...
    'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/pwm_output', ...
    'IOInterfaceMapping', '[0]');

% Set Outport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug1', ...
    'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug1', ...
    'IOInterfaceMapping', '[1]');

% Set Outport HDL parameters
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug2', ...
    'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]');
hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug2', ...
    'IOInterfaceMapping', '[2]');


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx ISE', ...
    'TargetWorkflow','FPGA Turnkey');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.RunTaskVerifyWithHDLCosimulation = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskPerformLogicSynthesis = true;
hWC.RunTaskPerformMapping = true;
hWC.RunTaskPerformPlaceAndRoute = true;
hWC.RunTaskGenerateProgrammingFile = true;
hWC.RunTaskProgramTargetDevice = false;

% Set Properties related to Create Project Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';

% Set Properties related to Perform Mapping Task
hWC.SkipPreRouteTimingAnalysis = true;

% Set Properties related to Perform Place and Route Task
hWC.IgnorePlaceAndRouteErrors = false;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is turnkey_workflow_example.m, at the command line, enter:

turnkey_workflow_example.m

Configure and Run IP Core Generation Workflow with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is an IP core generation workflow script that targets the Altera Cyclone V SoC development kit and uses the Altera Quartus II synthesis tool.

Open and view your exported HDL workflow script.

% Export Workflow Configuration Script
% Generated with MATLAB 8.6 (R2015b) at 14:42:16 on 08/07/2015
% Parameter Values:
%     Filename  : 'S:\ip_core_gen_workflow_example.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'hdlcoder_led_blinking/led_counter'

%% Load the Model
load_system('hdlcoder_led_blinking');

%% Model HDL Parameters
% Set Model HDL parameters
hdlset_param('hdlcoder_led_blinking', ...
    'HDLSubsystem', 'hdlcoder_led_blinking/led_counter');
hdlset_param('hdlcoder_led_blinking', 'OptimizationReport', 'on');
hdlset_param('hdlcoder_led_blinking', ...
    'ReferenceDesign', 'Default system (Qsys 14.0)');
hdlset_param('hdlcoder_led_blinking', 'ResetType', 'Synchronous');
hdlset_param('hdlcoder_led_blinking', 'ResourceReport', 'on');
hdlset_param('hdlcoder_led_blinking', 'SynthesisTool', 'Altera QUARTUS II');
hdlset_param('hdlcoder_led_blinking', 'SynthesisToolChipFamily', 'Cyclone V');
hdlset_param('hdlcoder_led_blinking', 'SynthesisToolDeviceName', '5CSXFC6D6F31C6');
hdlset_param('hdlcoder_led_blinking', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoder_led_blinking', ...
    'TargetPlatform', 'Altera Cyclone V SoC development kit - Rev.D');
hdlset_param('hdlcoder_led_blinking', 'Traceability', 'on');
hdlset_param('hdlcoder_led_blinking', 'Workflow', 'IP Core Generation');

% Set SubSystem HDL parameters
hdlset_param('hdlcoder_led_blinking/led_counter', ...
    'ProcessorFPGASynchronization', 'Free running');

% Set Inport HDL parameters
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', ...
    'IOInterface', 'AXI4');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', ...
    'IOInterfaceMapping', 'x"100"');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', ...
    'IOInterfaceOptions', {'RegisterInitialValue', 5});

% Set Inport HDL parameters
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', ...
    'IOInterface', 'AXI4');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', ...
    'IOInterfaceMapping', 'x"104"');
hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction, ...
    'IOInterfaceOptions', {'RegisterInitialValue', 1});

% Set Outport HDL parameters
hdlset_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterface', 'External Port');

% Set Outport HDL parameters
hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', 'IOInterface', 'AXI4');
hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', ...
    'IOInterfaceMapping', 'x"108"');
hdlset_param('hdlcoder_led_blinking/led_counter/Read back, ...
    'IOInterfaceOptions', {'RegisterInitialValue', 3});

%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Altera QUARTUS II', ...
    'TargetWorkflow','IP Core Generation');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskGenerateSoftwareInterface = false;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskProgramTargetDevice = false;

% Set Properties related to Generate RTL Code And IP Core Task
hWC.IPCoreRepository = '';
hWC.GenerateIPCoreReport = true;

% Set Properties related to Create Project Task
hWC.Objective = hdlcoder.Objective.AreaOptimized;

% Set Properties related to Generate Software Interface Model Task
hWC.OperatingSystem = '';
hWC.AddLinuxDeviceDriver = false;

% Set Properties related to Build FPGA Bitstream Task
hWC.RunExternalBuild = true;
hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('hdlcoder_led_blinking/led_counter', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is ip_core_workflow_example.m, at the command line, enter:

ip_core_gen_workflow_example.m

Configure and Run Simulink Real-Time FPGA I/O Workflow for ISE-Based Boards with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a Simulink Real-Time FPGA I/O workflow script that targets the Speedgoat IO331 board that uses the Xilinx ISE synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB 9.5 (R2018b Prerelease) at 18:14:14 on 08/05/2018
% This script was generated using the following parameter values:
%     Filename  : 'C:\Users\ggnanase\Desktop\R2018b\18b_models\ipcore_timing_failure\hdlworkflow_IO331.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'sfir_fixed/symmetric_fir'
% To view changes after modifying the workflow, run the following command:
% >> hWC.export('DUT','sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system('sfir_fixed');

%% Restore the Model to default HDL parameters
%hdlrestoreparams('sfir_fixed/symmetric_fir');

%% Model HDL Parameters
%% Set Model 'sfir_fixed' HDL parameters
hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx ISE');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Spartan6');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc6slx150');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'fgg676');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-3');
hdlset_param('sfir_fixed', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('sfir_fixed', 'TargetFrequency', 75);
hdlset_param('sfir_fixed', 'TargetPlatform', 'Speedgoat IO331');
hdlset_param('sfir_fixed', 'Workflow', 'Simulink Real-Time FPGA I/O');


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx ISE','TargetWorkflow','Simulink Real-Time FPGA I/O');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';
hWC.ReferenceDesignToolVersion = '';
hWC.IgnoreToolVersionMismatch = false;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCode = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskPerformLogicSynthesis = true;
hWC.RunTaskPerformMapping = true;
hWC.RunTaskPerformPlaceAndRoute = true;
hWC.RunTaskGenerateProgrammingFile = true;
hWC.RunTaskGenerateSimulinkRealTimeInterface = true;

% Set properties related to 'RunTaskCreateProject' Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';

% Set properties related to 'RunTaskPerformMapping' Task
hWC.SkipPreRouteTimingAnalysis = true;

% Set properties related to 'RunTaskPerformPlaceAndRoute' Task
hWC.IgnorePlaceAndRouteErrors = false;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('sfir_fixed/symmetric_fir', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is slrt_workflow_example.m, at the command line, enter:

slrt_workflow_example.m

Configure and Run Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a Simulink Real-Time FPGA I/O workflow script that targets the Speedgoat IO333-325K board that uses the Xilinx Vivado synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB 9.5 (R2018b Prerelease) at 18:14:33 on 08/05/2018
% This script was generated using the following parameter values:
%     Filename  : 'C:\Users\ggnanase\Desktop\R2018b\18b_models\ipcore_timing_failure\hdlworkflow_IO333.m'
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : 'sfir_fixed/symmetric_fir'
% To view changes after modifying the workflow, run the following command:
% >> hWC.export('DUT','sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system('sfir_fixed');

%% Restore the Model to default HDL parameters
%hdlrestoreparams('sfir_fixed/symmetric_fir');

%% Model HDL Parameters
%% Set Model 'sfir_fixed' HDL parameters
hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Kintex7');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7k325t');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'ffg900');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-2');
hdlset_param('sfir_fixed', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('sfir_fixed', 'TargetFrequency', 100);
hdlset_param('sfir_fixed', 'TargetPlatform', 'Speedgoat IO333-325K');
hdlset_param('sfir_fixed', 'Workflow', 'Simulink Real-Time FPGA I/O');


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','Simulink Real-Time FPGA I/O');

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';
hWC.ReferenceDesignToolVersion = '2017.4';
hWC.IgnoreToolVersionMismatch = false;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskGenerateSimulinkRealTimeInterface = true;

% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task
hWC.IPCoreRepository = '';
hWC.GenerateIPCoreReport = true;
hWC.GenerateIPCoreTestbench = false;
hWC.CustomIPTopHDLFile = '';
hWC.AXI4RegisterReadback = false;
hWC.IPDataCaptureBufferSize = '128';

% Set properties related to 'RunTaskCreateProject' Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';
hWC.EnableIPCaching = true;

% Set properties related to 'RunTaskBuildFPGABitstream' Task
hWC.RunExternalBuild = false;
hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;
hWC.CustomBuildTclFile = '';
hWC.ReportTimingFailure = hdlcoder.ReportTiming.Error;

% Validate the Workflow Configuration Object
hWC.validate;

%% Run the workflow
hdlcoder.runWorkflow('sfir_fixed/symmetric_fir', hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is slrt_workflow_example.m, at the command line, enter:

slrt_workflow_example.m

Documentation

hdlcoder.WorkflowConfig class

Description

Construction

Name-Value Pair Arguments

SynthesisTool — Synthesis tool name 'Xilinx Vivado' (default) | 'Altera QUARTUS II' | 'Xilinx ISE'

TargetWorkflow — Specify the target workflow 'Generic ASIC/FPGA' (default) | 'FPGA Turnkey' | 'IP Core Generation' | 'FPGA-in-the-Loop' | 'Simulink Real-Time FPGA I/O'

Properties

ProjectFolder — Folder for generated project files '' (default) | character vector

Objective — Synthesis tool objective hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized

RunTaskGenerateRTLCodeAndTestbench — Enable task to generate code and test bench true (default) | false

RunTaskVerifyWithHDLCosimulation — Enable task to verify generated code with HDL cosimulation true (default) | false

RunTaskCreateProject — Enable task to create synthesis tool project true (default) | false

RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesis true (default) | false

RunTaskPerformMapping — Enable task to map synthesized logic to target device true (default) | false

RunTaskPerformPlaceAndRoute — Enable task to run place and route process true (default) | false

RunTaskRunSynthesis — Enable task to launch Xilinx Vivado® and run synthesis true (default) | false

RunTaskRunImplementation — Enable task to launch Xilinx Vivado and run implementation true (default) | false

RunTaskAnnotateModelWithSynthesisResult — Enable task to analyze timing information and highlight critical paths true (default) | false

GenerateRTLCode — Generate HDL code true (default) | false

GenerateTestbench — Generate HDL test bench false (default) | true

GenerateValidationModel — Generate validation model false (default) | true

AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project '' (default) | character vector

SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logical false (default) | true

IgnorePlaceAndRouteErrors — Ignore place and route errors false (default) | true

CriticalPathSource — Critical path source 'pre-route' (default) | 'post-route'

CriticalPathNumber — Number of critical paths to annotate 1 (default) | 2 | 3

ShowAllPaths — Show all critical paths false (default) | true

ShowDelayData — Annotate cumulative timing delay on each critical path true (default) | false

ShowUniquePaths — Show only the first instance of a critical path false (default) | true

ShowEndsOnly — Show only endpoints of each critical path false (default) | true

ProjectFolder — Folder for generated project files '' (default) | character vector

RunTaskGenerateRTLCodeAndTestbench — Enable task to generate code and test bench true (default) | false

RunTaskVerifyWithHDLCosimulation — Enable task to verify generated code with HDL cosimulation true (default) | false

RunTaskBuildFPGAInTheLoop — Enable task to generate a model that contains a FIL block and a testbench around the FIL block true (default) | false

GenerateRTLCode — Generate HDL code true (default) | false

GenerateTestbench — Generate HDL test bench false (default) | true

GenerateValidationModel — Generate validation model false (default) | true

IPAddress — IP address of FPGA board '192.168.0.2' (default) | character vector

MACAddress — MAC address of FPGA board '00-0A-35-02-21-8A' (default) | character vector

SourceFiles — Additional HDL source files for verification '' (default) | character vector

Connection — JTAG or Ethernet connection 'JTAG' (default) | 'Ethernet'

RunExternalBuild — Run build process externally true (default) | false

ProjectFolder — Folder for generated project files '' (default) | character vector

Objective — Synthesis tool objective hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized

RunTaskGenerateRTLCode — Enable task to generate RTL code and HDL top-level wrapper true (default) | false

RunTaskCreateProject — Enable task to create synthesis tool project true (default) | false

RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesis true (default) | false

RunTaskPerformMapping — Enable task to map synthesized logic to target device true (default) | false

RunTaskPerformPlaceAndRoute — Enable task to run place and route process true (default) | false

RunTaskRunSynthesis — Enable task to launch Xilinx Vivado and run synthesis true (default) | false

RunTaskRunImplementation — Enable task to launch Xilinx Vivado and run implementation true (default) | false

RunTaskGenerateProgrammingFile — Enable task to generate FPGA programming file true (default) | false

RunTaskProgramTargetDevice — Enable task to program target device true (default) | false

AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project '' (default) | character vector

SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logical false (default) | true

IgnorePlaceAndRouteErrors — Ignore place and route errors false (default) | true

ProjectFolder — Folder for generated project files '' (default) | character vector

ReferenceDesignToolVersion — Current reference design tool version character vector

IgnoreToolVersionMismatch — Ignore mismatch in reference design tool version false (default) | true

RunTaskGenerateRTLCodeAndIPCore — Enable task to generate code and IP core true (default) | false

RunTaskCreateProject — Enable task to create embedded system tool project true (default) | false

RunTaskGenerateSoftwareInterface — Enable task to generate software interface true (default) | false

GenerateSoftwareInterfaceModel — Generate software interface model true (default) | false

GenerateSoftwareInterfaceScript — Generate software interface script true (default) | false

RunTaskBuildFPGABitstream — Enable task to generate bitstream for embedded system true (default) | false

RunTaskProgramTargetDevice — Enable task to program connected target device false (default) | true

IPCoreRepository — IP core repository folder path '' (default) | character vector

GenerateIPCoreReport — Generate HTML documentation for the IP core true (default) | false

Objective — Synthesis tool objective hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized

EnableIPCaching — Create IP cache to reduce reference design synthesis time false (default) | true

OperatingSystem — Operating system '' (default) | character vector

AddLinuxDeviceDriver — Add IP core device driver false (default) | true

RunExternalBuild — Run build process externally true (default) | false

ReportTimingFailure — Report timing failures as warnings or errors hdlcoder.ReportTimingFailure.Error (default) | hdlcoder.ReportTimingFailure.Warning

TclFileForSynthesisBuild — Use custom or default synthesis tool build script hdlcoder.BuildOption.Default (default) | hdlcoder.BuildOption.Custom

CustomBuildTclFile — Custom synthesis tool build script file '' (default) | character vector

ProjectFolder — Folder for generated project files '' (default) | character vector

ReferenceDesignToolVersion — Current reference design tool version character vector

IgnoreToolVersionMismatch — Ignore mismatch in reference design tool version false (default) | true

`SynthesisTool` — Synthesis tool name
`'Xilinx Vivado'` (default) | `'Altera QUARTUS II'` | `'Xilinx ISE'`

`TargetWorkflow` — Specify the target workflow
`'Generic ASIC/FPGA'` (default) | `'FPGA Turnkey'` | `'IP Core Generation'` | `'FPGA-in-the-Loop'` | `'Simulink Real-Time FPGA I/O'`

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

`RunTaskGenerateRTLCodeAndTestbench` — Enable task to generate code and test bench
`true` (default) | `false`

`RunTaskVerifyWithHDLCosimulation` — Enable task to verify generated code with HDL cosimulation
`true` (default) | `false`

`RunTaskCreateProject` — Enable task to create synthesis tool project
`true` (default) | `false`

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`

`RunTaskRunSynthesis` — Enable task to launch Xilinx Vivado^® and run synthesis
`true` (default) | `false`

`RunTaskRunImplementation` — Enable task to launch Xilinx Vivado and run implementation
`true` (default) | `false`

`RunTaskAnnotateModelWithSynthesisResult` — Enable task to analyze timing information and highlight critical paths
`true` (default) | `false`

`GenerateRTLCode` — Generate HDL code
`true` (default) | `false`

`GenerateTestbench` — Generate HDL test bench
`false` (default) | `true`

`GenerateValidationModel` — Generate validation model
`false` (default) | `true`

`AdditionalProjectCreationTclFiles` — Additional project creation Tcl files to include in your synthesis project
`''` (default) | character vector

`SkipPreRouteTimingAnalysis` — Skip pre-route timing analysis `logical`
`false` (default) | `true`

`IgnorePlaceAndRouteErrors` — Ignore place and route errors
`false` (default) | `true`

`CriticalPathSource` — Critical path source
`'pre-route'` (default) | `'post-route'`

`CriticalPathNumber` — Number of critical paths to annotate
1 (default) | 2 | 3

`ShowAllPaths` — Show all critical paths
`false` (default) | `true`

`ShowDelayData` — Annotate cumulative timing delay on each critical path
`true` (default) | `false`

`ShowUniquePaths` — Show only the first instance of a critical path
`false` (default) | `true`

`ShowEndsOnly` — Show only endpoints of each critical path
`false` (default) | `true`

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

`RunTaskGenerateRTLCodeAndTestbench` — Enable task to generate code and test bench
`true` (default) | `false`

`RunTaskVerifyWithHDLCosimulation` — Enable task to verify generated code with HDL cosimulation
`true` (default) | `false`

`RunTaskBuildFPGAInTheLoop` — Enable task to generate a model that contains a FIL block and a testbench around the FIL block
`true` (default) | `false`

`GenerateRTLCode` — Generate HDL code
`true` (default) | `false`

`GenerateTestbench` — Generate HDL test bench
`false` (default) | `true`

`GenerateValidationModel` — Generate validation model
`false` (default) | `true`

`IPAddress` — IP address of FPGA board
`'192.168.0.2'` (default) | character vector

`MACAddress` — MAC address of FPGA board
`'00-0A-35-02-21-8A'` (default) | character vector

`SourceFiles` — Additional HDL source files for verification
`''` (default) | character vector

`Connection` — JTAG or Ethernet connection
`'JTAG'` (default) | `'Ethernet'`

`RunExternalBuild` — Run build process externally
`true` (default) | `false`

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

`RunTaskGenerateRTLCode` — Enable task to generate RTL code and HDL top-level wrapper
`true` (default) | `false`

`RunTaskCreateProject` — Enable task to create synthesis tool project
`true` (default) | `false`

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`

`RunTaskRunSynthesis` — Enable task to launch Xilinx Vivado and run synthesis
`true` (default) | `false`

`RunTaskRunImplementation` — Enable task to launch Xilinx Vivado and run implementation
`true` (default) | `false`

`RunTaskGenerateProgrammingFile` — Enable task to generate FPGA programming file
`true` (default) | `false`

`RunTaskProgramTargetDevice` — Enable task to program target device
`true` (default) | `false`

`AdditionalProjectCreationTclFiles` — Additional project creation Tcl files to include in your synthesis project
`''` (default) | character vector

`SkipPreRouteTimingAnalysis` — Skip pre-route timing analysis `logical`
`false` (default) | `true`

`IgnorePlaceAndRouteErrors` — Ignore place and route errors
`false` (default) | `true`

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

`ReferenceDesignToolVersion` — Current reference design tool version
character vector

`IgnoreToolVersionMismatch` — Ignore mismatch in reference design tool version
`false` (default) | `true`

`RunTaskGenerateRTLCodeAndIPCore` — Enable task to generate code and IP core
`true` (default) | `false`

`RunTaskCreateProject` — Enable task to create embedded system tool project
`true` (default) | `false`

`RunTaskGenerateSoftwareInterface` — Enable task to generate software interface
`true` (default) | `false`

`GenerateSoftwareInterfaceModel` — Generate software interface model
`true` (default) | `false`

`GenerateSoftwareInterfaceScript` — Generate software interface script
`true` (default) | `false`

`RunTaskBuildFPGABitstream` — Enable task to generate bitstream for embedded system
`true` (default) | `false`

`RunTaskProgramTargetDevice` — Enable task to program connected target device
`false` (default) | `true`

`IPCoreRepository` — IP core repository folder path
`''` (default) | character vector

`GenerateIPCoreReport` — Generate HTML documentation for the IP core
`true` (default) | `false`

`Objective` — Synthesis tool objective
`hdlcoder.Objective.None` (default) | `hdlcoder.Objective.SpeedOptimized` | `hdlcoder.Objective.AreaOptimized` | `hdlcoder.Objective.CompileOptimized`

`EnableIPCaching` — Create IP cache to reduce reference design synthesis time
`false` (default) | `true`

`OperatingSystem` — Operating system
`''` (default) | character vector

`AddLinuxDeviceDriver` — Add IP core device driver
`false` (default) | `true`

`RunExternalBuild` — Run build process externally
`true` (default) | `false`

`ReportTimingFailure` — Report timing failures as warnings or errors
`hdlcoder.ReportTimingFailure.Error` (default) | `hdlcoder.ReportTimingFailure.Warning`

`TclFileForSynthesisBuild` — Use custom or default synthesis tool build script
`hdlcoder.BuildOption.Default` (default) | `hdlcoder.BuildOption.Custom`

`CustomBuildTclFile` — Custom synthesis tool build script file
`''` (default) | character vector

`ProjectFolder` — Folder for generated project files
`''` (default) | character vector

`ReferenceDesignToolVersion` — Current reference design tool version
character vector

`IgnoreToolVersionMismatch` — Ignore mismatch in reference design tool version
`false` (default) | `true`

`RunTaskGenerateRTLCodeAndIPCore` — Enable task to generate code and IP core
`true` (default) | `false`

`RunTaskGenerateRTLCode` — Enable task to generate RTL code and HDL top-level wrapper
`true` (default) | `false`

`RunTaskCreateProject` — Enable task to create embedded system tool project
`true` (default) | `false`

`RunTaskPerformLogicSynthesis` — Enable task to launch synthesis tool and run logic synthesis
`true` (default) | `false`

`RunTaskPerformMapping` — Enable task to map synthesized logic to target device
`true` (default) | `false`

`RunTaskPerformPlaceAndRoute` — Enable task to run place and route process
`true` (default) | `false`