Utilize RAM resources in your FPGA design using HDL Coder™.

Use the subsystem level streaming optimization in HDL Coder.

Use the subsystem level sharing optimization in HDL Coder.

How HDL Coder™ manages the execution of operations in the context of clock rate pipelining. By default, if resource sharing is applied in a region of the design operating at the fastest base sample rate, then a local multi-rate architecture is synthesized, as described in Resource Sharing For Area Optimization. If the shared resources are operating at a slower sample rate and clock rate pipelining is enabled, then the code generator synthesizes a single-rate architecture, which is described in this example.

Improve opportunities for resource sharing to optimize your model design by making certain modifications to your design. Resource sharing is an HDL Coder optimization that improves area utilization in the design on the target FPGA device. The optimization identifies multiple functionally equivalent resources and replaces them with a single resouce. For more information, see Resource Sharing.

Automatically identify and replace recurring patterns by using the Clone Detector App. Consequently, it also improves opportunities for optimizing the model by using resource sharing. The Clone Detector App refactors models by identifying clones in a design and replacing clones with links to subsystem blocks in a library. This example uses a model that has already been modified for optimal resource sharing by using the Clone Detector App. To learn more about these modifications, see "Improve Resource Sharing with Design Modifications."