RTL Customization Parameters for RAMs
This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.
Initialize all RAM blocks
Enable or suppress generation of initial signal value for RAM blocks. If you specify a nonzero initial value for the RAM, this setting is ignored.
Settings
Default: On
On For RAM blocks, generate initial values of
'0'for both the RAM signal and the output temporary signal.
OffFor RAM blocks, do not generate initial values for either the RAM signal or the output temporary signal.
Tip
This parameter applies to these RAM blocks in the HDL Coder > HDL RAMs Block Library in the Simulink Library Browser:
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
Dual Rate Dual Port RAM
Command-Line Information
Property:
InitializeBlockRAM |
| Type: character vector |
Value:
'on' | 'off' |
Default:
'on' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
RAM Architecture
Select RAM architecture with clock enable, or without clock enable, for all RAMs in DUT subsystem.
Settings
Default:
RAM with clock enable
Select one of the following options from the menu:
RAM with clock enable: Generate RAMs with clock enable.Generic RAM without clock enable: Generate RAMs without clock enable.
Command-Line Information
Property:
RAMArchitecture |
| Type: character vector |
Value:
'WithClockEnable' |
'WithoutClockEnable' |
Default:
'WithClockEnable' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.