FIR Decimation HDL Optimized

Finite impulse response (FIR) decimation filter—optimized for HDL code generation

Library:
DSP System Toolbox HDL Support / Filtering

Description

The FIR Decimation HDL Optimized block implements a polyphase FIR decimation filter that is optimized for HDL code generation. The block provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.

The block accepts scalar or vector input. When you use vector input, the decimation factor must be an integer multiple of the vector size. The block uses a single-rate implementation. The output is scalar and a valid signal indicates which samples are valid after decimation. The waveform shows an input vector of four samples and a decimation factor of eight. The output sample is valid every second cycle.

The block provides two filter structures. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel^® and Xilinx^® DSP blocks. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

The block implements one filter for each sample in the input vector. The block then shares this filter between the polyphase subfilters by interleaving the subfilter coefficients in time.

For a FIR decimation filter with an input size greater the decimation factor or a serial HDL implementation (scalar input only), use the FIR Decimation block instead of this block.

Ports

Input

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`data` — Input data
scalar | vector

Input data must be a real- or complex-valued scalar or vector. When you use vector input, the decimation factor must be an integer multiple of the vector size. The vector size must be less than or equal to 64.

When the input data type is an integer type or a fixed-point type, the block uses fixed-point arithmetic for internal calculations.

double and single data types are supported for simulation, but not for HDL code generation.

`valid` — Validity of input data
scalar

When valid is 1, the block captures the data from the data input port.

Data Types: Boolean

`reset` — Control signal that clears data path state
scalar

When reset is 1, the block stops the current calculation and clears the internal state of the filter. The reset signal is synchronous and clears the data path and control path states. For more reset considerations, see Tips.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

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`data` — Filtered output data
scalar

Filtered output data, returned as a real- or complex-valued scalar. When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the Output parameter on the Data Types tab specifies the output data type.

The output valid signal indicates which samples are valid after decimation.

Data Types: fixed point | single | double
Complex Number Support: Yes

`valid` — Validity of output data
scalar

The block sets valid to 1 with each valid data returned on the data output port.

Data Types: Boolean

Parameters

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Main

`Coefficients` — Discrete FIR filter coefficients
`fir1(35,0.4)` (default) | real- or complex-valued vector

Discrete FIR filter coefficients, specified as a real- or complex-valued vector. You can specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floating-point type, the block casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can set the data type for the coefficients on the Data Types tab.

Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0])

`Filter structure` — HDL filter architecture
`Direct form systolic` (default) | `Direct form transposed`

Specify the HDL filter architecture as one of these structures:

Direct form systolic — This architecture provides a fully parallel filter implementation that makes efficient use of Intel and Xilinx DSP blocks.
Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications.

Both implementations share resources by interleaving the subfilter coefficients over one filter implementation for each sample in the input vector.

The block implements a polyphase decomposition filter using Discrete FIR Filter HDL Optimized blocks. For architecture details, see the Fully Parallel Systolic Architecture and the Fully Parallel Transposed Architecture sections on the Discrete FIR Filter HDL Optimized block reference page.

`Decimation factor` — Decimation factor
2 (default) | integer greater than two

Specify an integer decimation factor greater than two. When you use vector input, the decimation factor must be an integer multiple of the vector size.

Data Types

`Rounding mode` — Rounding mode for type-casting the output
`Floor` (default) | `Ceiling` | `Convergent` | `Nearest` | `Round` | `Zero`

Rounding mode for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Rounding Modes.

`Saturate on integer overflow` — Overflow handling for type-casting the output
`off` (default) | `on`

Overflow handling for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Overflow Handling.

`Coefficients` — Data type of filter coefficients
`Inherit: Same word length as input` (default) | `<data type expression>`

The block casts the filter coefficients to this data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the block ignores this parameter.

The recommended data type for this parameter is Inherit: Same word length as input.

The block returns a warning or error if either of these conditions occur.

The coefficients data type does not have enough fractional length to represent the coefficients accurately.
The coefficients data type is unsigned, and the coefficients include negative values.

You can disable or control the severity of these data type messages from the model Configuration Parameters, by modifying the Diagnostics > Type Conversion > Detect precision loss parameter.

`Output` — Data type of filter output
`Inherit: Inherit via internal rule` (default) | `Inherit: Same word length as input` | `<data type expression>`

The block casts the output of the filter to this data type. The quantization uses the settings of the Rounding mode and Overflow mode parameters. When the input data type is floating point, the block ignores this parameter.

The block increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L)).

Because the coefficient values limit the potential growth, usually the actual full-precision internal word length is smaller than WF.

Control Ports

`Enable reset input port` — Option to enable reset input port
`off` (default) | `on`

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

`Use HDL global reset` — Option to connect data path registers to generated HDL global reset signal
`off` (default) | `on`

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink^®. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see Tips.

Model Examples

FIR Decimation for FPGA

Decimate streaming samples using a hardware-friendly polyphase FIR filter. It also shows the differences between the dsp.FIRDecimator object and the hardware-friendly streaming interface of the FIR Decimation HDL Optimized block.

Tips

Reset Behavior

By default, the FIR Decimation HDL Optimized block connects the generated HDL global reset to only the control path registers. The two reset parameters, Enable reset input port and Use HDL global reset, connect a reset signal to the data path registers. Because of the additional routing and loading on the reset signal, resetting data path registers can reduce synthesis performance .
The Enable reset input port parameter enables the reset port on the block. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.
The Use HDL global reset parameter connects the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters. Depending on your device, using the global reset might move registers out of the DSP blocks and increase resource use.
When you select the Enable reset input port and Use HDL global reset parameters together, the global and local reset signals clear the control and data path registers.

Reset Considerations for Generated Test Benches

FPGA-in-the-loop initialization provides a global reset but does not automatically provide a local reset. With the default reset parameters, the data path registers that are not reset can result in FPGA-in-the-loop (FIL) mismatches if you run the FIL model more than once without resetting the board. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the Simulink FIL test bench.
The generated HDL test bench provides a global reset but does not automatically provide a local reset. With the default reset parameters and the default register reset Configuration Parameters, the generated HDL code includes an initial simulation value for the data path registers. However, if you are concerned about X-propagation in your design, you can set the HDL Code Generation > Global Settings > Coding style > No-reset register initialization parameter in Configuration Parameters to Do not initialize. In this case, with the default block reset parameters, the data path registers that are not reset can cause X-propagation on the data path at the start of HDL simulation. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the generated HDL test bench.

Algorithms

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The block implements a polyphase filter bank where the filter coefficients are decomposed into Decimation factor subfilters. If the filter length is not divisible by the Decimation factor parameter value, then the block zero-pads the coefficients.

The diagram shows the polyphase filter bank with scalar input and the Decimation factor parameter set to four. The four sets of decomposed coefficients are interleaved in time over a single subfilter.

The next diagram shows the polyphase filter bank for an input vector of four values and the Decimation factor parameter set to eight. Each of the four subfilters has two sets of coefficients interleaved in time.

Each subfilter is implemented with a Discrete FIR Filter HDL Optimized block. The adder at the output is pipelined to accommodate higher synthesis frequencies. For architecture details, see the Fully Parallel Systolic Architecture, Fully Parallel Transposed Architecture, and Complex Multipliers sections on the Discrete FIR Filter HDL Optimized block reference page.

Note

The output of the FIR Decimation HDL Optimized block does not match the output from the FIR Decimation block sample-for-sample. This difference is mainly because of the phase that the samples are applied across the subfilters. To match the FIR Decimation block, apply Decimation factor – 1 zeroes to the FIR Decimation HDL Optimized block at the start of the data stream.

The FIR Decimation block also uses slightly different data types for full-precision calculations. The different data types can also introduce differences in output values if the values overflow the internal data types.

Performance

This table shows the post-synthesis resource utilization for the HDL code generated for the default FIR decimation filter using scalar input, a decimation factor of eight, 16-bit input, and 16-bit coefficients. The synthesis targets a Xilinx ZC-706 (XC7Z045ffg900-2) FPGA. The Global HDL reset typeparameter is Synchronous, and the Minimize clock enables parameter is selected. The reset port is disabled, so only the control path registers are connected to the generated global HDL reset.

Resource	Uses
LUT	676
Slice Reg	878
Slice	257
Xilinx LogiCORE DSP48	5

After place and route, the maximum clock frequency of the design is 526 MHz.

For the same filter with a four-element input vector, the filter uses these resources.

Resource	Uses
LUT	322
Slice Reg	2351
Slice	502
Xilinx LogiCORE DSP48	20

After place and route, the maximum clock frequency of the design is 518 MHz.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

FIR Decimation HDL Optimized

Description