NR Polar Decoder
Perform polar decoding according to the 5G NR standard
- Library:
Wireless HDL Toolbox / Error Detection and Correction
Description
The NR Polar Decoder block implements a streaming polar decoder with hardware-friendly control signals. You can configure the block to use downlink or uplink coding schemes as defined by the 5G NR standard. The 5G NR standard uses polar codes for channel coding of the DCI, UCI, and BCH transmit channels.
This block implements a CRC-aided successive-cancellation list decoder. This
implementation matches the performance of the 5G Toolbox™ function nrPolarDecode with a list length of
two. This block also performs CRC decoding of the message, equivalent to the nrCRCDecode function. The block detects DCI messages from the values of
K and E, and automatically prepends 1s to the
message, equivalent to the padCRC input argument of the nrPolarDecode function.
This block does not support parity-aided codes.
Because the latency of this operation can vary, the block provides an output signal, nextFrame, that indicates when the block is ready to accept new inputs.
Ports
Input
Output
Parameters
Model Examples
Algorithms
This block implements a CRC-aided successive-cancellation list decoder that uses a list
length of two. The decoder iterates over all LLRs in the tree to reach a decision for a bit
and then uses that decision to decode the next bit. The deinterleaving step is included only
when you set the Link direction parameter to
Downlink.
This diagram shows the architecture of the polar decoder.
The Configuration stage is used when the K and E
input port values change. The block computes the locations of the information bits and passes
them to the Decision stage. Because the mapping patterns are computed as needed, rather than
stored in hardware, the block supports all K and E
values within the supported range. The Configuration stage also computes the interleave
pattern when you set the Link direction parameter to
Downlink.
When you set the Configuration source parameter to
Property, the K and E
parameter values are constants, so the decoder does not implement the Configuration stage. In
this case, the block includes static lookup tables that contain the precomputed
configuration.
To minimize computations for each decode, the Tree Memory stores the probability of each node being a one or a zero. Each iteration updates only the LLRs that have changed. The Core decoding stage uses the LLR update equations from [3].
The Decision stage checks the LLR value against the expected locations of information bits and frozen bits and returns a hard decision to the Tree Memory. If the bit is expected to be frozen, the Decision stage returns a hard decision of zero and updates the probabilities of related paths. The Path Memory reconstructs the two most likely paths from the hard decision results and passes the paths and scores to the next stage. The Path Selection stage computes the CRC for both paths and then chooses the path that passes the CRC. If both CRCs fail, the block returns the path that has the higher score.
This implementation matches the performance of the 5G Toolbox function nrPolarDecode with a list length of
two. Because the block uses fixed-point internal types, any differences are a result of
quantization. This plot shows the block performance when using 6-bit LLR inputs.
Latency
The table shows example latencies of the NR Polar Decoder block for each N, when decoding for uplink and downlink channels. N is the power-of-two encoded message length determined from the values of K and E.
| N | Uplink Latency | Downlink Latency |
|---|---|---|
| 32 | 379 | N/A |
| 64 | 653 | 739 |
| 128 | 1179 | 1265 |
| 256 | 2236 | 2322 |
| 512 | 4374 | 4460 |
| 1024 | 9242 | Not applicable |
The exact latency varies based on the values of K and E. The latency is longer for frames where the K and E input port values change and the block must compute the new configuration. Because the latency varies, use the output nextFrame control signal to determine when the block is ready for a new input frame.
This waveform shows how the latency varies with the K and E input port values. When the input K and E port values are 132 and 256, the block has a latency of 2369 cycles from the input start signal to the output nextFrame. When the K and E port values change to 54 and 124, the latency changes to 1274 cycles.
References
[1] 3GPP TS 38.211. "NR; Physical channels and modulation." 3rd Generation Partnership Project; Technical Specification Group Radio Access Network. URL: https://www.3gpp.org.
[2] Arikan, Erdal. "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels." IEEE Transactions on Information Theory 55, no. 7 (July 2009): 3051–73. https://doi.org/10.1109/TIT.2009.2021379.
[3] Balatsoukas-Stimming, Alexios, Mani Bastani Parizi, and Andreas Burg. "LLR-Based Successive Cancellation List Decoding of Polar Codes." IEEE Transactions on Signal Processing 63, no. 19 (October 2015): 5165–79. https://doi.org/10.1109/TSP.2015.2439211.