NR LDPC Decoder

Decode input data using layered belief propagation with min-sum approximation algorithm

Library:
Wireless HDL Toolbox / Error Detection and Correction

Description

The NR LPDC Decoder block implements a low-density parity-check (LDPC) decoder with hardware-friendly control signals. The block accepts punctured log-likelihood ratio (LLR) values, a ctrl bus, a base graph number, and lifting sizes. The block outputs decoded bits, a ctrl bus, lifting sizes, and a nextFrame port. Because, the latency of the block varies, the block provides the nextFrame output port, which indicates when the block is ready to accept new inputs.

This block implements the layered belief propagation with min-sum approximation algorithm. This implementation matches that of the 5G Toolbox™ function nrLDPCDecode.

The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block for channel coding of downlink and uplink shared channels and paging channel according to 5G New Radio (NR) standard TS 38.212 [1].

Ports

Input

expand all

`data` — Input LLR values
vector

Input log-likelihood ratio (LLR) values, specified as a column vector of size 64.

Input data must be of a signed fixed-point data type with a word length from 4 to 16 bits. For more information on how to specify the input data, see Specifying Input Data.

Data Types: int8 | int16 | fixed point

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the input data port is valid

Data Types: bus

`bgn` — Base graph number
Boolean scalar

Base graph number, specified as a Boolean scalar. When this value is 0, the block applies bgn 1. When this value is 1, the block applies bgn 2. For more information about bgn 1 and bgn 2, see section 5.3.2, TS 38.212 [1].

Data Types: Boolean

`liftingSize` — Input lifting size
scalar

Input lifting size, specified as a scalar.

For an invalid liftingSize value, the block discards the current frame and waits for the new frame.

For more information about the supported lifting size values, see section 5.3.2, TS 38.212 [1].

Data Types: uint16

`iter` — Number of iterations
scalar

Number of iterations, specified as a integer scalar in the range from 1 to 63.

If you specify a iter as a value greater than 63, the block automatically sets the iter value to 8 and performs the decoding operation.

Dependencies

To enable this port, set the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

expand all

`data` — Decoded output data bits
vector

Decoded output data bits, returned as a column vector of size 64.

The block outputs data bits in a similar format as the input LLR values. Extract these output data bits in the similar format for further processing.

Data Types: Boolean

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the output frame
end — Indicates the end of the output frame
valid — Indicates that the data on the output data port is valid

Data Types: bus

`liftingSize` — Output lifting size
scalar

Output lifting size, returned as a scalar.

Data Types: uint16

`nextFrame` — Ready for new inputs
Boolean scalar

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

Parameters

expand all

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

Select the source for number of iterations.

You can set number of iterations with an input port or by specifying a value for the parameter.

Select Property to enable the Source for number of iterations parameter.
Select Input port to enable the iter port.

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

Specify the number of iterations.

Dependencies

To enable this parameter, set the Source for number of iterations parameter to Property.

Model Examples

LDPC Encode and Decode of Streaming Data

Simulate the NR LDPC Encoder and NR LDPC Encoder Decoder blocks. In this example, the hardware-optimized results of these blocks are compared with respective functions in the 5G Toolbox™.

Open Script

More About

expand all

Specifying Input Data

The input data for the block must be specified as a column vector of size 64. You must provide inputs as an integer number of ceil(liftingSize/64) clock cycles.

The total number of clock cycles that the block requires to receive a frame of LLR values for decoding is equal to n x ceil(liftingSize/64), where n is the number of columns in the parity check matrix. n depends on the base graph number, specified by the bgn input port. When the bgn port value is 0, the block sets n to 66. When the bgn port value is 1, the block sets n to 50.

The following sections show how the block accepts input LLR values based on the liftingSize and bgn port values.

When the lifting size value is less than 64 and the bgn value is equal to 0

For a liftingSize value of 2, the block accepts the first two LLR input bits in each clock cycle and ignores the remaining 62 elements in that clock cycle. The total number of clock cycles the block requires to receive a frame of LLR values is 66.

Input LLR Values	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	66 Clock Cycles
`data[0]`	L₀	L₂	L₄	L₆	...	L₁₃₀
`data[1]`	L₁	L₃	L₅	L₇	...	L₁₃₁
...	X	X	X	X	X	X
`data[63]`	X	X	X	X	X	X

When the liftingSize value is greater than 64 and the bgn value is equal to 0

For a liftingSize value of 104, the block accepts 104 LLR values in two clock cycles: first 64 LLRs in the first clock cycle and 40 LLRs in the second clock cycle. The block ignores the remaining 24 elements in the second clock cycle. The total number of clock cycles the block requires to receive input LLR values is 132.

Input LLR Values	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	...	131 Clock Cycles	132 Clock Cycles
`data[0]`	L₀	L₆₄	L₁₀₄	L₁₆₈	...	...	L₆₇₆₀	L₆₈₂₄
`data[1]`	L₁	L₆₅	L₁₀₅	L₁₆₉	...	...	L₆₇₆₁	L₆₈₂₅
	...	...	...		...	...	...	...
...	...	L₁₀₃	...	L₂₀₇	...	...	...	L₆₈₆₃
...	...	X	...	X	...	...	...	X
`data[63]`	L₆₃	X	L₁₆₇	X	...	...	L₆₈₂₃	X

In the above tables, L_n elements represent LLR bits, and X represents ignored values.

Algorithms

expand all

This figure shows the architecture block diagram of the NR LDPC Decoder block. The Functional Processing Unit block calculates the variable node (VN) messages and check node (CN) messages based on the layered belief propagation with min-sum approximation algorithm. For more information, see Algorithm (5G Toolbox).

The implementation of the block matches the performance that of the 5G Toolbox function nrLDPCDecode. This plot shows the performance of the block when using a 6-bit LLR input.

Latency

The latency varies based on the values of bgn, liftingSize, and iter. Since the latency varies, use the nextFrame control signal to determine when the block is ready for a new input frame.

The latency of the block is equal to iter x t + n x ceil(liftingSize/64) + 18. In this calculation, t is the number of clock cycles taken for each iteration, and n is the number of columns in the parity check matrix.

For a bgn port value of 0, t is 1046, and n is 66. For a bgn port value of 1, t is 772, and n is 50.

This figure shows a sample output of the NR LDPC Decoder block with latency. In this case, the bgn, liftingSize, and iter port values are set to 0, 384, and 8, respectively. The latency of the block is 8782 clock cycles.

This figure shows a sample output of the NR LDPC Decoder block with latency. In this case, the bgn, liftingSize, and iter port values are set to 1, 48, and 8, respectively. The latency of the block is 6244 clock cycles, and the same value is captured for two frames.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block when it is configured with bgn, liftingSize, and iter ports and has input LLR values of data type fixdt(1,4,0). The generated HDL is targeted to Xilinx^® Zynq^®Ultrascale+™ RFSoC Evaluation Board. The design achieves a clock frequency of 186.15 MHz.

Resource	Number Used
Slice LUTs	117, 237
Slice Registers	121, 186
DSPs	0
Block RAMs	19

References

[1] 3GPP TS 38.212. “NR; Multiplexing and channel coding.” 3rd Generation Partnership Project; Technical Specification Group Radio Access Network.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. www.doi.org/10.1109/TIT.1962.1057683.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

NR LDPC Decoder

Description

Ports

Input

`data` — Input LLR values
vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`bgn` — Base graph number
Boolean scalar

`liftingSize` — Input lifting size
scalar

`iter` — Number of iterations
scalar

Dependencies

Output

`data` — Decoded output data bits
vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`liftingSize` — Output lifting size
scalar

`nextFrame` — Ready for new inputs
Boolean scalar

Parameters

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

Dependencies

Model Examples

LDPC Encode and Decode of Streaming Data

More About

Specifying Input Data

When the lifting size value is less than 64 and the bgn value is equal to 0

When the liftingSize value is greater than 64 and the bgn value is equal to 0

Algorithms

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

See Also

Introduced in R2020a

Wireless HDL Toolbox Documentation

Support

Documentation

NR LDPC Decoder

Description

Ports

Input

data — Input LLR values vector

ctrl — Control signals accompanying sample stream samplecontrol bus

bgn — Base graph number Boolean scalar

liftingSize — Input lifting size scalar

iter — Number of iterations scalar

Dependencies

Output

data — Decoded output data bits vector

ctrl — Control signals accompanying sample stream samplecontrol bus

liftingSize — Output lifting size scalar

nextFrame — Ready for new inputs Boolean scalar

Parameters

Source for number of iterations — Source selection for number of iterations Property (default) | Input port

Number of iterations — Number of iterations 8 (default) | integer in the range from 1 to 63

Dependencies

Model Examples

LDPC Encode and Decode of Streaming Data

More About

Specifying Input Data

When the lifting size value is less than 64 and the bgn value is equal to 0

When the liftingSize value is greater than 64 and the bgn value is equal to 0

Algorithms

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

See Also

Introduced in R2020a

Wireless HDL Toolbox Documentation

Support

`data` — Input LLR values
vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`bgn` — Base graph number
Boolean scalar

`liftingSize` — Input lifting size
scalar

`iter` — Number of iterations
scalar

`data` — Decoded output data bits
vector

`ctrl` — Control signals accompanying sample stream
`samplecontrol` bus

`liftingSize` — Output lifting size
scalar

`nextFrame` — Ready for new inputs
Boolean scalar

`Source for number of iterations` — Source selection for number of iterations
`Property` (default) | `Input port`

`Number of iterations` — Number of iterations
`8` (default) | integer in the range from 1 to 63

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.