Simulink Real-Time FPGA I/O Modules
You can generate an FPGA programming file and Simulink Real-Time FPGA I/O interface for deployment on a Speedgoat board. See IP Core Generation Workflow for Speedgoat I/O Modules.
Classes
hdlcoder.Board | Board registration object that describes SoC custom board |
hdlcoder.ReferenceDesign | Reference design registration object that describes SoC reference design |
hdlcoder.WorkflowConfig | Configure HDL code generation and deployment workflows |
Topics
FPGA Programming and Configuration
How select and run an automated code generation and synthesis workflow for a Speedgoat target device
IP Core Generation Workflow for Speedgoat I/O Modules
Learn how to use the IP Core Generation workflow with Speedgoat I/O modules and embed the IP core into the reference design.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware
Deploy Simscape™ Plant Models to Speedgoat FPGA I/O Modules
How to deploy the generated HDL code from Simscape™ models to Speedgoat IO modules.
Speedgoat FPGA Support with HDL Workflow Advisor
Implementing Simulink algorithms on FPGAs.
Related Information
Troubleshooting
Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
