Custom Reference Design

Create your own custom reference design for integrating the generated IP core into the target SoC device, Speedgoat board, or the standalone FPGA boards

You can create your own custom reference design in MATLAB® and use HDL Coder™ to integrate the IP core into your reference design.

Classes

hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows

Functions

socExportReferenceDesignExport custom reference design for HDL Workflow Advisor

Topics

Board and Reference Design Registration System

System for defining and registering boards and reference designs.

Register a Custom Board

Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.

Register a Custom Reference Design

Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.

Define Custom Parameters and Callback Functions for Custom Reference Design

Learn how to define custom parameters and custom callback functions for your custom reference design.

Customize Reference Design Dynamically Based on Reference Design Parameters

Learn how to customize the reference design dynamically by using the CustomizeReferenceDesignFcn method.

Define and Add IP Repository to Custom Reference Design

Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.

Define Multiple AXI Master Interfaces in Reference Designs to access DUT AXI4 Slave Interface

Learn how you can specify multiple AXI Master interfaces in the custom reference design to access HDL DUT IP AXI4 slave interface.

Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces

Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.

Export Custom Reference Design from SoC Model (SoC Blockset)

Use the socExportReferenceDesign function to export a custom reference design from an SoC Blockset™ model.

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

Define Custom Board and Reference Design for Zynq Workflow

Define Custom Board and Reference Design for Zynq Workflow

Define and register a custom board and reference design in the Zynq® workflow.

Open Script
Define Custom Board and Reference Design for Intel SoC Workflow

Define Custom Board and Reference Design for Intel SoC Workflow

Define and register a custom board and reference design in the HDL Coder™ Intel SoC workflow.

Open Script
Authoring a Reference Design for Audio System on a Zynq Board

Authoring a Reference Design for Audio System on a Zynq Board

Build a reference design to run an audio algorithm and access audio input and output on a Zynq® board.

Open Script
Authoring a Reference Design for Audio System on a ZYBO Board

Authoring a Reference Design for Audio System on a ZYBO Board

Build a reference design to run an audio algorithm and access audio input and output on ZYBO board.

Open Script
Running an audio filter on live audio input using a Zynq board

Running an audio filter on live audio input using a Zynq board

Model an audio system and implement it on a Zynq board using an audio reference design.

Open Script
Running Audio Filter with Multiple AXI4-Stream Channels on ZedBoard

Running Audio Filter with Multiple AXI4-Stream Channels on ZedBoard

Run an audio filter with multiple AXI4-Stream channels on ZedBoard.

Open Script
Using JTAG MATLAB as AXI Master to control HDL Coder generated IP Core

Using JTAG MATLAB as AXI Master to control HDL Coder generated IP Core

Illustrates how to automatically insert the JTAG MATLAB as AXI Master IP into your reference design, and use MATLAB to prototype your HDL Coder generated FPGA IP Core.

Open Script
Export Custom Reference Design

Export Custom Reference Design

Export a custom reference design from an SoC model by using the Soc Blockset™ socExportReferenceDesign function. After creating the custom reference design, use the HDL Workflow Advisor tool from HDL Coder™ to integrate an IP core into the reference design.

Open Example
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