IP Core Generation

Generate an HDL IP core that contains HDL code for deployment on standalone FPGA boards, Speedgoat boards, Xilinx® Zynq®-7000 platform, or Intel® SoC Devices

HDL Coder™ can generate an IP core that contains the HDL source code and the C header files for integrating the IP core into your EDK project, and then program the target hardware.

Classes

hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows

Topics

Hardware Software Co-Design and HDL Workflow

Hardware-Software Co-Design Workflow for SoC Platforms

High-level workflow steps for targeting an SoC platform

Run HDL Workflow with a Script

Export, import, or configure an HDL Workflow CLI command script.

Getting Started with the HDL Workflow Advisor

Learn the basics of the HDL Workflow Advisor and how to run various tasks.

Model and Debug Test Point Signals with HDL Coder™

An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.

Program Target FPGA Boards or SoC Devices

How to program the target Intel or Xilinx Hardware

IP Core Generation

Custom IP Core Generation

Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.

Multirate IP Core Generation

Learn various example designs that use multiple sample rates with IP Core Generation workflow.

Custom IP Core Report

You generate an HTML custom IP core report by default when you generate a custom IP core.

Generate Board-Independent HDL IP Core from Simulink Model

When you open the HDL Workflow Advisor and run the IP Core Generation workflow for your Simulink® model, you can specify a generic Xilinx platform or a generic Intel platform.

Generate Board-Independent IP Core from MATLAB Algorithm

Board-independent IP core generation from MATLAB®

Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces

Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.

Processor and FPGA Synchronization

In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:

Synchronization of Global Reset Signal to IP Core Clock Domain

Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain.

IP Caching for Faster Reference Design Synthesis

Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

Getting Started with the HDL Workflow Command-Line Interface

Getting Started with the HDL Workflow Command-Line Interface

Use the HDL Workflow Advisor to run HDL workflows from the command-line and the 'Export to script' functionality.

Open Script
Save Target Hardware Settings in Model

Save Target Hardware Settings in Model

Save your target hardware settings in a Simulink® model.

Open Script
IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip

IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip

Illustrates how to model an I2C controller using an I2C Master controller modeled using Stateflow™ blocks for configuring the audio codec chip.

Open Script
Using IP Core Generation Workflow from MATLAB: LED Blinking

Using IP Core Generation Workflow from MATLAB: LED Blinking

Use MATLAB® HDL Workflow Advisor to generate a custom HDL IP core which blinks LEDs on FPGA board. The generated IP core can be used on Xilinx® Zynq® platform, or on any Xilinx FPGA with MicroBlaze processor.

Open Script
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