You can generate HDL code for your plant model that you developed by using Simscape™ blocks and then deploy the generated code to standalone FPGA boards, or to FPGAs onboard the Speedgoat hardware, SoC devices, and so on. By deploying the plant model to an FPGA board, you can accelerate the simulation of your plant model and simulate the model in real time by using Hardware-in-the-Loop (HIL) simulations.

Before you generate HDL code, use the sschdladvisor function to generate an HDL implementation model from Simscape switched linear models. Switched linear models are models that contain blocks such as diodes or switches. These blocks are defined by a linear relationship such as V = IR where R can switch between two or more values depending on the state of the diodes or switches.

After you generate the HDL implementation model, you can use HDL Coder™ to generate code for this model and deploy the generated code to target platforms by using the HDL Workflow Advisor. When you generate the HDL implementation model, you can specify whether to generate the implementation model with single-precision or double-precision floating-point data types. You can also specify insertion of a validation logic in the implementation model to verify whether the HDL implementation numerically matches the original Simscape algorithm.