Verify Generated Code from Simulink Model Using HDL Test Bench

This example shows how to generate a HDL test bench and verify the generated code for your design. The example assumes that you have already generated HDL code for your model. This example illustrates how to verify the generated code for a simple up counter. To learn more about this counter model and how to generate HDL code, see Generate HDL Code from Simulink Model.

Note

If you haven't already generated HDL code, you can still open this model and generate the HDL test bench. Before generating the test bench, HDL Coder™ runs code generation to make sure that there is at least one successful code generation run before generating the testbench.

Simple Up Counter Model

Open Script

Open this model to see a simple up counter. The model counts up from zero to a threshold value and then wraps back to zero. In this model, the threshold value is set to 15. You can change the threshold value by changing the value of the Constant block that is input to the count_threshold port. The Enable signal specifies whether the counter should count up or hold the previous value. The Enable signal is set to 1 which means that the counter counts upwards continuously.

open_system('hdlcoder_simple_up_counter.slx')
set_param('hdlcoder_simple_up_counter', 'SimulationCommand', 'Update')

How to Verify the Generated Code

This example illustrates how to generate a HDL test bench to simulate and verify the generated HDL code for your design. You can also verify the generated HDL code from your model using these methods:

Verification Method	For More Information
Validation Model	Generated Model and Validation Model
HDL Cosimulation (requires HDL Verifier™)	Cosimulation
SystemVerilog DPI Test Bench	SystemVerilog DPI Test Bench
FPGA-in-the-Loop	FPGA-in-the-Loop

What is a HDL Test Bench?

To verify the functionality of the HDL code that you generated for the DUT, generate a HDL test bench. A test bench includes:

Stimulus data generated by signal sources connected to the entity under test.
Output data generated by the entity under test. During a test bench run, this data is compared to the outputs of the VHDL^® model, for verification purposes.
Clock, reset, and clock enable inputs to drive the entity under test.
A component instantiation of the entity under test.
Code to drive the entity under test and compare its outputs to the expected data.

You can simulate the generated test bench and script files with the Mentor Graphics^® ModelSim^® simulator.

Generate HDL Test Bench

Depending on whether you generated VHDL or Verilog code, generate VHDL or Verilog test bench code. The test bench code drives the HDL code that you generated for the DUT. By default, the HDL code and the test bench code are written to the same target folder hdlsrc relative to the current folder.

For the up counter model, the HDL_DUT Subsystem is the DUT. To generate the testbench, select this Subsystem. You cannot generate a HDL testbench for an entire model.

In the Apps tab, select HDL Coder. The HDL Code tab appears.
Select the DUT Subsystem in your model, and make sure that this Subsystem name appears in the Code for option. To remember the selection, you can pin this option. Click Generate Testbench.

By default, HDL Coder generates VHDL testbench code in the target hdlsrc folder.

To generate Verilog testbench code for the counter model:

In the HDL Code tab, click Settings.
In the HDL Code Generation pane, for Language, select Verilog. Leave other settings to the default.
In the HDL Code Generation > Test Benchpane, click Generate Test Bench.

View HDL Test Bench Files

If you haven't already generated code for your model, HDL Coder compiles the model and generates HDL code before generating the test bench. Depending on model display options such as port data types, the model can change in appearance after code generation.
As test bench generation proceeds, HDL Coder displays progress messages. The process should complete with the message
```
### HDL TestBench Generation Complete.
```
After generating the test bench, you see the generated files in the hdlsrc folder. For example, if you generated a test bench for the HDL_DUT Subsystem in your up counter model, the folder contains:
- HDL_DUT_tb.vhd: VHDL test bench code, with generated test and output data.
  Note
  If you generated Verilog test bench code, the generated file is HDL_DUT_tb.v.
- HDL_DUT_tb_pkg.vhd: Package file for VHDL test bench code. This file is not generated if you specified Verilog as the target language.
- HDL_DUT_tb_compile.do: Mentor Graphics ModelSim compilation script (vcom commands). This script compiles and loads the entity to be tested (HDL_DUT.vhd) and the test bench code (HDL_DUT_tb.vhd).
- HDL_DUT_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.
To view the generated test bench code in the MATLAB^® Editor, double-click the HDL_DUT_tb.vhd or HDL_DUT_tb.v file in the Current Folder.

Run Simulation and Verify Generated HDL Code

To verify the simulation results, you can use the Mentor Graphics ModelSim simulator. Make sure that you have already installed Mentor Graphics ModelSim.

To launch the simulator, use the vsim function. This command shows how to open the simulator by specifying the path to the executable:

vsim('vsimdir','C:\Program Files\ModelSim\questasim\10.6b\win64\vsim.exe')

To compile and run a simulation of the generated model and test bench code, use the scripts that are generated by HDL Coder. Following example illustrates the commands that compile and simulate the generated test bench for the hdlcoder_simple_up_counter/HDL_DUT Subsystem.

Open the Mentor Graphics ModelSim software and navigate to the folder that has the generated code files and the scripts.
Use the generated compilation script to compile and load the generated model and text bench code. For example, if you generated a test bench for the hdlcoder_simple_up_counter/HDL_DUT Subsystem, run this command to compile the generated code.
```
QuestaSim>do HDL_DUT_tb_compile.do
```
Use the generated simulation script to execute the simulation. The following listing shows the command and responses. You can ignore any warning messages. The test bench termination message indicates that the simulation has run to completion without comparison errors. For example, if you generated a test bench for the hdlcoder_simple_up_counter/HDL_DUT Subsystem, run this command to simulate the generated code.
```
QuestaSim>do HDL_DUT_tb_sim.do
```
The simulator optimizes your design and displays the results of simulating your HDL design in a wave window. if you don't see the simulation results, open the wave window. The simulation script displays inputs and outputs in the model including the clock , reset, and clock enable signals in the wave window.

You can now view the signals and verify that the simulation results match the functionality of your original design. After verifying, close the Mentor Graphics ModelSim simulator, and then close the files that you have opened in the MATLAB Editor.

Deploy Generated HDL Code on Target Device

After you verified the functionality of your HDL design, you can deploy the generated code on a target FPGA device. For deployment, you use the Simulink HDL Workflow Advisor. To learn how more, see HDL Code Generation and FPGA Synthesis Using Simulink HDL Workflow Advisor.

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