HDL Designer Series Command Reference

Version 2018.1

Description: Use these commands to setup and run tasks in batch mode.
When specifying a task, be aware that it is a tcl list, with each element of the list being a level of hierarchy
As each element is separated with whitespace, be sure to escape whitespace that is part of a task name

For example, if you have a flow arranged like this:

Flow 1
  |--- Tool A
  |--- Tool B
  |--- Flow 2
         |--- Tool C
         |--- Tool D

This refers to "Flow 1" : {Flow\ 1}
This refers to "Tool A" : {Flow\ 1 Tool\ A}
This refers to "Tool D" : {Flow\ 1 Flow\ 2 Tool\ D}

runTask (args)
setCompileAlways (enable)
setupTask (args)

runTask (args)
Run a task
Example:
# run DesignChecker on Verilog view "asm" for "xmit_rcv_control" design unit. runTask DesignChecker "uart_v" "xmit_rcv_control" "xmit_rcv_control" "xmit_rcv_control/asm.am"

Argument: args Option names and values.
<taskName> Specify the task run. Must be specified.

[library [unit [view [pathName] ] ] ] Specifies the view to run the task on. If none are specified uses design root.

-user If HDS finds a user and a team task with the same name, pick the user task. This is the default.

-team If HDS finds a user and a team task with the same name, pick the team task.

setCompileAlways (enable)
Enable or disable incremental compilation for all incremental compilers
Argument: enable ON|OFF : Set the global compile always switch (defaults to off)

setupTask (args)
Setup options for a task
Argument: args Option names and values.
<taskName> Specify the task to apply these setup options to. Must be specified.

-setting <name> <value> Changes the value of the setting given by <name> on the specified task.

-single Changes the hierarchy depth to be used when running the task to single level.

-hierarchical Changes the hierarchy depth to be used when running the task to hierarchy through blocks.

-throughCpt Changes the hierarchy depth to be used when running the task to hierarchy through components.

-user If HDS finds a user and a team task with the same name, pick the user task. This is the default.

-team If HDS finds a user and a team task with the same name, pick the team task.

runTask (args)
Run a task
Example: # run DesignChecker on Verilog view "asm" for "xmit_rcv_control" design unit. runTask DesignChecker "uart_v" "xmit_rcv_control" "xmit_rcv_control" "xmit_rcv_control/asm.am"
Argument: args	Option names and values.
<taskName>	Specify the task run. Must be specified.
[library [unit [view [pathName] ] ] ]	Specifies the view to run the task on. If none are specified uses design root.
-user	If HDS finds a user and a team task with the same name, pick the user task. This is the default.
-team	If HDS finds a user and a team task with the same name, pick the team task.

setCompileAlways (enable)
Enable or disable incremental compilation for all incremental compilers
Argument: enable	ON\|OFF : Set the global compile always switch (defaults to off)

setupTask (args)
Setup options for a task
Argument: args	Option names and values.
<taskName>	Specify the task to apply these setup options to. Must be specified.
-setting <name> <value>	Changes the value of the setting given by <name> on the specified task.
-single	Changes the hierarchy depth to be used when running the task to single level.
-hierarchical	Changes the hierarchy depth to be used when running the task to hierarchy through blocks.
-throughCpt	Changes the hierarchy depth to be used when running the task to hierarchy through components.
-user	If HDS finds a user and a team task with the same name, pick the user task. This is the default.
-team	If HDS finds a user and a team task with the same name, pick the team task.

HDL Designer Series Command Reference

Version 2018.1

runTask (args)

setCompileAlways (enable)

setupTask (args)

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