HDL Designer Series Command Reference

Version 2018.1

Description
Associated with an implementation of an entity. Corresponds to a VHDL architecture, a Verilog module and an HDS structural or leaf graphics file


$architecture configure (args)

with no arguments lists the names and values of all options
with one argument lists the value of the specified option
The following options are available:
class : identifies the object as an architecture
name : name of the declaration itself
fullName : fully qualified name including those of parent objects
startLine : the line number where the declaration begins in the source file
refName : Name that can be to refer to the object when running tasks or accessing properties
Argument: args see above

$architecture contexts ()

Obtain the contexts referenced.
Returns: A list of contexts.

$architecture entity ()

Get the entity associated with the architecture, see entityRefApi.tcl
Returns: The entity object.

$architecture file ()

Obtain the file containing the object.
Returns: A single object, see fileRefApi.tcl

$architecture frame ()

obtains the root frame of the architecture, see architectureFrameRefApi.tcl.
Returns: The root frame.

$architecture instances ()

Gets all the instances in all frames of the architecture, see instanceRefApi.tcl

$architecture packages ()

Obtain the packages referenced.
Returns: A list of packages, see packageHeaderRefApi.tcl or an empty list if the declaration is not VHDL.

$architecture views ()

Obtain the packages referenced.
Returns: A list of packages, see packageHeaderRefApi.tcl or an empty list if the declaration is not VHDL.


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