Chart

Implement control logic with finite state machine

Library:
Stateflow

Description

A finite state machine is a representation of an event-driven (reactive) system. In an event-driven system, the system responds to an event by making a transition from one state (mode) to another. This transition occurs if the condition defining the change is true.

A Stateflow^® chart is a graphical representation of a finite state machine. States and transitions form the basic elements of the system. You can also represent stateless flow charts.

For example, you can use Stateflow charts to control a physical plant in response to events such as a temperature and pressure sensors, clocks, and user-driven events.

You can also use a state machine to represent the automatic transmission of a car. The transmission has these operating states: park, reverse, neutral, drive, and low. As the driver shifts from one position to another, the system makes a transition from one state to another, for example, from park to reverse.

A Stateflow chart can use MATLAB or C as the action language to implement control logic.

Ports

Input

expand all

`Port_1` — Input port
scalar | vector | matrix

When you create input data in the Symbols pane, Stateflow creates input ports. The input data that you create has a corresponding input port that appears once you create data.

Output

expand all

`Port_1` — Output port
scalar | vector | matrix

When you create output data in the Symbols pane, Stateflow creates output ports. The output data that you create has a corresponding output port that appears once you create data.

Parameters

expand all

Parameters on the Code Generation tab require Simulink^® Coder™ or Embedded Coder^®.

Main

`Show port labels` — Select how to display port labels
`FromPortIcon` (default) | `FromPortBlockName` | `SignalName`

Select how to display port labels on the Chart block icon.

none: Do not display port labels.
FromPortIcon: If the corresponding port icon displays a signal name, display the signal name on the Chart block. Otherwise, display the port block name.
FromPortBlockName: Display the name of the corresponding port block on the Chart block.
SignalName: If a signal name exists, display the name of the signal connected to the port on the Chart block. Otherwise, display the name of the corresponding port block.

Programmatic Use

Parameter: ShowPortLabels

Type: character vector

Value: 'FromPortIcon' | 'FromPortBlockName' | 'SignalName'

Default: 'FromPortIcon'

`Read/Write permissions` — Select access to contents of chart
`ReadWrite` (default) | `ReadOnly` | `NoReadOrWrite`

Control user access to the contents of the chart.

ReadWrite: Enable opening and modification of chart contents.
ReadOnly: Enable opening but not modification of the chart. If the chart resides in a block library, you can create and open links to the chart and can make and modify local copies of the chart but you cannot change the permissions or modify the contents of the original library instance.
NoReadOrWrite: Disable opening or modification of chart. If the chart resides in a library, you can create links to the chart in a model but you cannot open, modify, change permissions, or create local copies of the chart.

Programmatic Use

Parameter: Permissions

Type: character vector

Value: 'ReadWrite' | 'ReadOnly' | 'NoReadOrWrite'

Default: 'ReadWrite'

`Treat as atomic unit` — Control execution of a subsystem as one unit
off (default) | on

When determining the execution order of block methods, causes Simulink to treat the chart as a unit.

off: When determining block method execution order, treat all blocks in the chart as being at the same level in the model hierarchy as the chart. This hierarchy treatment can cause the execution of methods of blocks in the chart to be interleaved with the execution of methods of blocks outside the chart.
on: When determining the execution order of block methods, treat the chart as a unit. For example, when Simulink needs to compute the output of the chart, Simulink invokes the output methods of all the blocks in the chart before invoking the output methods of other blocks at the same level as the chart block.

Dependency

If you select this parameter, you enable the Minimize algebraic loop occurrences, Sample time, and Function packaging parameters. Function packaging requires the Simulink Coder software.

Programmatic Use

Parameter: TreatAsAtomicUnit

Type: character vector

Value: 'off' | 'on'

Default: 'off'

`Minimize algebraic loop occurrences` — Control elimination of algebraic loops
off (default) | on

off: Do not try to eliminate any artificial algebraic loops that include the atomic subchart.
on: Try to eliminate any artificial algebraic loops that include the atomic subchart.

Dependency

To enable this parameter, select the Treat as atomic unit parameter.

Programmatic Use

Parameter: MinAlgLoopOccurrences

Type: character vector

Value: 'off' | 'on'

Default: 'off'

`Sample time` — Specify time interval
`-1` (default) | `[Ts 0]`

Specify whether all blocks in this chart must run at the same rate or can run at different rates.

If the blocks in the chart can run at different rates, specify the chart sample time as inherited (-1).
If all blocks must run at the same rate, specify the sample time corresponding to this rate as the value of the Sample time parameter.
If any of the blocks in the chart specify a different sample time (other than -1 or inf), Simulink displays an error message when you update or simulate the model. For example, suppose all the blocks in the chart must run 5 times a second. To ensure this time, specify the sample time of the chart as 0.2. In this example, if any of the blocks in the chart specify a sample time other than 0.2, -1, or inf, Simulink displays an error when you update or simulate the model.

-1: Specify inherited sample time. If the blocks in the chart can run at different rates, use this sample time.
[Ts 0]: Specify periodic sample time.

Dependency

To enable this parameter, select the Treat as atomic unit parameter.

Programmatic Use

Parameter: SystemSampleTime

Type: character vector

Value: '-1' | '[Ts 0]'

Default: '-1'

`Treat as grouped when propagating variant conditions` — Control treating subsystem as unit
`on` (default) | `off`

When propagating variant conditions from Variant Source blocks or to Variant Sink blocks, causes Simulink to treat the chart as a unit.

on: Simulink treats the chart as a unit when propagating variant conditions from Variant Source blocks or to Variant Sink blocks. For example, when Simulink computes the variant condition of the chart, it propagates that condition to all the blocks in the chart.
off: Simulink treats all blocks in the chart as being at the same level in the model hierarchy as the chart itself when determining their variant condition.

Programmatic Use

Parameter: TreatAsGroupedWhenPropagatingVariantConditions

Type: character vector

Value: 'on' | 'off'

Default: 'on'

Code Generation

`Function packaging` — Select code format
`Auto` (default) | `Inline` | `Nonreusable function` | `Reusable function`

Select the generated code format for an atomic (nonvirtual) subchart.

Auto

Simulink Coder chooses the optimal format for your system based on the type and number of instances of the chart that exist in the model.

Inline

Simulink Coder inlines the chart unconditionally.

Nonreusable function

Simulink Coder explicitly generates a separate function in a separate file. Charts with this setting generate functions that might have arguments depending on the Function interface parameter setting. You can name the generated function and file using parameters Function name and File name (no extension). These functions are not reentrant.

Reusable function

Simulink Coder generates a function with arguments that allows reuse of chart code when a model includes multiple instances of the chart.

This option generates a function with arguments that allows chart code to be reused in the generated code of a model reference hierarchy that includes multiple instances of a chart across referenced models. In this case, the chart must be in a library.

Tips

When you want multiple instances of a chart represented as one reusable function, you can designate each one of them as Auto or as Reusable function. It is best to use one because using both creates two reusable functions, one for each designation. The outcomes of these choices differ only when reuse is not possible. Selecting Auto does not allow for control of the function or file name for the chart code.
The Reusable function and Auto options both determine whether multiple instances of a chart exist and the code can be reused. The options behave differently when it is impossible to reuse the code. In this case, Auto yields inlined code, or if circumstances prohibit inlining, separate functions for each chart instance.
If you select the Reusable function while your generated code is under source control, set File name options to Use subsystem name, Use function name, or User specified. Otherwise, the names of your code files change whenever you modify your model, which prevents source control on your files.

Dependency

This parameter requires Simulink Coder.
To enable this parameter, select Treat as atomic unit.
Setting this parameter to Nonreusable function or Reusable function enables the following parameters:
- Function name options
- File name options
- Memory section for initialize/terminate functions (requires Embedded Coder and an ERT-based system target file)
- Memory section for execution functions (requires Embedded Coder and an ERT-based system target file)
Setting this parameter to Nonreusable function enables Function with separate data (requires a license for Embedded Coder and an ERT-based system target file).

Programmatic Use

Parameter: RTWSystemCode

Type: character vector

Value: 'Auto' | 'Inline' | 'Nonreusable function' | 'Reusable function'

Default: 'Auto'

Model Examples

Design a Game by Using Stateflow

Implement the game of Tetris by using a Stateflow® chart. This model is a redesigned version of the classic Stateflow demo sf_tetris. The new design incorporates these programming paradigms: Parallel decomposition to separate pre- and post-processing tasks from the main game control logic.

Model an Elevator System by Using Atomic Subcharts

Model a two-car elevator system by using linked atomic subcharts in Stateflow®. The elevator system consists of a Simulink® model and a user interface (UI). The model contains two Stateflow charts: Elevator System models the core logic that delegates incoming requests from the UI to the nearest available elevator car. This chart contains a pair of atomic subcharts that implement identical logic for the cars.

Model a Fitness Tracker

Implement a fitness tracker by using temporal logic and messages.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

Active State Output

To generate an output port in the HDL code that shows the active state, in the Properties window of the chart, select Create output for monitoring. The output is an enumerated data type. See Simplify Stateflow Charts by Incorporating Active State Output.

Registered Output

To insert an output register that delays the chart output by a simulation cycle, use the OutputPipeline (HDL Coder) block property.

HDL Block Properties

ConstMultiplierOptimization	Canonical signed digit (CSD) or factored CSD optimization. The default is `none`. See also ConstMultiplierOptimization (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `off`. See also DistributedPipelining (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
InstantiateFunctions	Generate a VHDL^® `entity` or Verilog^® `module` for each function. The default is `off`. See also InstantiateFunctions (HDL Coder).
LoopOptimization	Unroll, stream, or do not optimize loops. The default is `none`. See also LoopOptimization (HDL Coder).
MapPersistentVarsToRAM	Map persistent arrays to RAM. The default is `off`. See also MapPersistentVarsToRAM (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
ResetType	Suppress reset logic generation. The default is `default`, which generates reset logic. See also ResetType (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
VariablesToPipeline	Warning `VariablesToPipeline` is not recommended. Use `coder.hdl.pipeline` (HDL Coder) instead. Insert a pipeline register at the output of the specified MATLAB^® variable or variables. Specify the list of variables as a character vector, with spaces separating the variables.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

To learn about restrictions of using charts, see Introduction to Stateflow HDL Code Generation (HDL Coder).

Documentation

Chart

Description

Ports

Input

Port_1 — Input port scalar | vector | matrix

Output

Port_1 — Output port scalar | vector | matrix

Parameters

Main

Show port labels — Select how to display port labels FromPortIcon (default) | FromPortBlockName | SignalName

Programmatic Use

Read/Write permissions — Select access to contents of chart ReadWrite (default) | ReadOnly | NoReadOrWrite

Programmatic Use

Treat as atomic unit — Control execution of a subsystem as one unit off (default) | on

Dependency

Programmatic Use

See also

Minimize algebraic loop occurrences — Control elimination of algebraic loops off (default) | on

Dependency

Programmatic Use

Sample time — Specify time interval -1 (default) | [Ts 0]

Dependency

Programmatic Use

Treat as grouped when propagating variant conditions — Control treating subsystem as unit on (default) | off

Programmatic Use

Code Generation

Function packaging — Select code format Auto (default) | Inline | Nonreusable function | Reusable function

Tips

Dependency

Programmatic Use

Model Examples

Design a Game by Using Stateflow

Model an Elevator System by Using Atomic Subcharts

Model a Fitness Tracker

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Topics

Stateflow Documentation

Support

`Port_1` — Input port
scalar | vector | matrix

`Port_1` — Output port
scalar | vector | matrix

`Show port labels` — Select how to display port labels
`FromPortIcon` (default) | `FromPortBlockName` | `SignalName`

`Read/Write permissions` — Select access to contents of chart
`ReadWrite` (default) | `ReadOnly` | `NoReadOrWrite`

`Treat as atomic unit` — Control execution of a subsystem as one unit
off (default) | on

`Minimize algebraic loop occurrences` — Control elimination of algebraic loops
off (default) | on

`Sample time` — Specify time interval
`-1` (default) | `[Ts 0]`

`Treat as grouped when propagating variant conditions` — Control treating subsystem as unit
`on` (default) | `off`

`Function packaging` — Select code format
`Auto` (default) | `Inline` | `Nonreusable function` | `Reusable function`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.