Logic Analyzer
Visualize, measure, and analyze transitions and states over time
Open the Logic Analyzer App
On the Simulink toolstrip Simulation tab, click the Logic Analyzer app button. If the button is not displayed, expand the review results app gallery. Your most recent choice for data visualization is saved across Simulink sessions.
To visualize referenced models, you must open the Logic Analyzer from the referenced model. You should see the name of the referenced model in the Logic Analyzer toolbar.
Examples
Select Signals to Analyze
The Logic Analyzer supports several methods for selecting data to visualize.
Select a signal in your model. When you select a signal, an ellipsis appears above the signal line. Hover over the ellipsis to view options and then select the Enable Data Logging option.
Right-click a signal in your model to open an options dialog box. Select the Log Selected Signals option.
Use any method to select multiple signal lines in your model. For example, use Shift+click to select multiple lines individually or CTRL+A to select all lines at once. Then, on the Signal tab, select the Log Signals button.
To visualize data in the Logic Analyzer, you must enable signal logging for the model. (Logging is on by default.) To enable signal logging, open Model Settings from the toolstrip, navigate to the Data Import/Export pane, and select Signal logging.
When you open the Logic Analyzer, all signals marked for logging are listed. You can add and delete waves from your Logic Analyzer while it is open. Adding and deleting signals does not disable logging, only removes the signal from the Logic Analyzer.
Modify Global Settings
Open the Logic Analyzer and select Settings from the toolstrip. A global settings dialog box opens. Any setting you change for an individual signal supersedes the global setting. The Logic Analyzer saves any setting changes with the model (Simulink) or System object™ (MATLAB®).
Set the display Radix of your signals as one of the following:
Hexadecimal— Displays values as symbols from zero to nine and A to FOctal— Displays values as numbers from zero to sevenBinary— Displays values as zeros and onesSigned decimal— Displays the signed, stored integer valueUnsigned decimal— Displays the stored integer value
Set the display Format as one of the following:
Automatic— Displays floating point signals inAnalogformat and integer and fixed-point signals inDigitalformat. Boolean signals are displayed as zero or one.Analog— Displays values as an analog plotDigital— Displays values as digital transitions
Set the display Time Units to one of the following:
Automatic— Uses a time scale appropriate to the time range shown in the current plotsecondsmillisecondsmicrosecondsnanosecondspicosecondsfemtoseconds
Set the Boolean Highlighting to one of the following:
NoneRows— Adds a highlighted background for the entire Boolean signal row.
Select Highlight boolean values to add highlighting to Boolean signals.
Gradient— Adds color highlighting to Boolean signals based on value. If the signal value istrue, the highlight fades out below. If the signal value isfalse, the signal fades out above. With this option, you can visually deduce the value of the signal.
Inspect the graphic for an explanation of the global settings: Wave Color, Axes
Color, Height, Font Size, and
Spacing. Font Size applies only to the text within the axes.
By default, when your simulation stops, the Logic Analyzer shows all the data for the simulation time on one screen. If you do not want this behavior, clear Fit to view at Stop. This option is disabled for long simulation times.
To display the short names of waves without path information, select Display short wave names.
You can expand fixed-point and integer signals and view individual bits. The Display Least Significant bit first option enables you to reverse the order of the displayed bits.
If you stream logged bus signals to the Logic Analyzer, you can display the names of the signals inside the bus using the Display bus element names option. To show bus element names:
Add the bus signal for logging.
In the Logic Analyzer settings, select the Display bus element names check box.
Run the simulation.
When you expand the bus signals, you will see the bus signal names.
Some special situations:
If the signal has no name, the Logic Analyzer shows the block name instead.
If the bus is a bus object, the Logic Analyzer shows the bus element names specified in the Bus Object Editor.
If one of the bus elements contains an array, each element of the array is appended with the element index.
If a bus element contains an array with complex elements, the real and complex values (
i) are split.
Bus signals passed through a Gain block are labeled
Gain(1),Gain(2),...Gain(n).If the bus contains an array of buses, the Logic Analyzer prepends the element name with the bus array index.
Modify Individual Wave Settings
Open the Logic Analyzer and select a wave by double-clicking the wave name. Then from the Wave tab, set parameters specific to the individual wave you selected. Any setting made on individual signals supersedes the global setting. To return individual wave parameters to the global settings, click Reset.
Delete and Restore Waves
Open the Logic Analyzer and select a wave by clicking the wave name.
From the Logic Analyzer toolstrip, click
. The wave is removed from the Logic
Analyzer.To restore the wave, from the Logic Analyzer toolstrip, click
.A divider named Restored Waves is added to the bottom of your channels, with all deleted waves placed below it.
Add Trigger
The Logic Analyzer trigger allows you to find data points based on certain conditions. This feature is useful for debugging or testing when you need to find a specific signal change.
Open the Logic Analyzer and select the Trigger tab.
To attach a signal to the trigger, select Attach Signals, then select the signal you want to trigger on. You can attach up to 20 signals to the trigger. Each signal can have only one triggering condition.
By default, the trigger looks for rising edges in the attached signals. You can set the trigger to look for rising or falling edges, bit sequences, or a comparison value. To change the triggering conditions, select Set Conditions.
If you add multiple signals to the trigger, control the trigger logic using the Operator option:
AND- match all conditions.OR- match any condition.
To control how many samples you see before triggering, set the Display Samples option. For example, if you set this option to
500, the Logic Analyzer tries to give you 500 samples before the trigger. Depending on the simulation, the Logic Analyzer may show more or fewer than 500 samples before the trigger. However, if the trigger is found before the 500th sample, the Logic Analyzer still shows the trigger.Control the trigger mode using Display Mode.
Once- The Logic Analyzer marks only the first location matching the trigger conditions and stops showing updates to the Logic Analyzer. If you want to reset the trigger, select Rearm Trigger. Relative to the current simulation time, the Logic Analyzer shows the next matching trigger event.Auto- The Logic Analyzer marks every location matching the trigger conditions.
Before running the simulation, select Enable Trigger. A blue cursor appears as time 0. Then, run the simulation. When a trigger is found, the Logic Analyzer marks the location with a locked blue cursor.
View Bit-Expanded Wave and Reverse Display Order of Bits
The Logic Analyzer enables you to bit-expand fixed-point and integer waves.
In the Logic Analyzer, click the arrow next to a fixed-point or integer wave to view the bits.
The least significant bit and the most significant bit are marked with lsb and msb next to the wave names.
Click Settings, and then select Display Least Significant bit first to reverse the order of the displayed bits.
Related Examples
- Programmable FIR Filter for FPGA (HDL Coder)
- Packet-Based ADS-B Transceiver
- Log Simulation Output for States and Data (Stateflow)
- View Stateflow States in the Logic Analyzer (Stateflow)
Limitations
Logging Settings
If you enable the configuration parameter Log Dataset data to file, you cannot stream logged data to the Logic Analyzer.
Signals marked for logging using
Simulink.sdi.markSignalForStreamingor visualized with a Dashboard Scope do not appear on the Logic Analyzer.You cannot visualize Data Store Memory block signals in the Logic Analyzer if you set the Log data store data parameter to on.
Input Signal Limitations
Signals marked for logging for the Logic Analyzer must have fewer than 8000 samples per simulation step.
The Logic Analyzer does not support frame-based processing.
Integers larger than 64 bits and fixed-point signals larger than 128 bits are not supported.
You may see performance degradation in the Logic Analyzer for large matrices (greater than 500 elements) and buses with more than 1000 signals.
The Logic Analyzer does not support Stateflow data output.
Graphical Settings
While the simulation is running, you cannot zoom, pan, or modify the trigger.
To visualize constant signals, in the settings, you must set the Format to
Digital. Constants marked for logging are visualized as a continuous transition.
| Mode | Supported | Notes and Limitations |
|---|---|---|
Normal | Yes | |
Accelerator | Yes | You cannot use the Logic Analyzer to visualize
signals in Model blocks
with Simulation mode set to
|
Rapid Accelerator | Yes | Data is not available in the Logic Analyzer during simulation. If you simulate a model with the simulation mode set to rapid accelerator, after simulation the following signals cannot be visualized in the Logic Analyzer:
|
Processor-in-the-loop (PIL) | No | |
Software-in-the-loop (SIL) | No | |
External | No |
For more information about these modes, see How Acceleration Modes Work.