Memory Transactions

Create shared memory system in SoC model

SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.

Blocks

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Memory ChannelStream data through a memory channel
Memory ControllerArbitrate memory transactions for one or more Memory Channel blocks
Memory Traffic GeneratorGenerate traffic towards memory controller
Register ChannelTiming model for transfer of register values
IP Core Register ReadModel register writes from software to hardware
Interrupt ChannelSend interrupt to processor from hardware
SoC Bus SelectorConvert bus to control signals
SoC Bus Creator Convert control signals to bus
Stream FIFOControl backpressure between hardware logic and upstream data interface
Video Stream FIFOControl backpressure between hardware logic and upstream video interface
Stream ConnectorConnect two IPs with data streaming interfaces
Video Stream ConnectorConnect two IPs with video streaming interfaces

Simulink Configuration Parameters

Hardware Implementation Pane

Topics

Memory and Register Data Transfers

Introduction to memory and register transfers.

External Memory Channel Protocols

Supported memory channel protocols and control signals.

AXI4-Stream Interface

How to design your model for AXI4-Stream vector or scalar interface generation.

Simplified AXI4 Master Interface

Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.

AXI4-Stream Video Interface

How to design your model for IP core generation with AXI4-stream video interfaces.

Related Information

Featured Examples

Histogram Equalization Using Video Frame Buffer

Histogram Equalization Using Video Frame Buffer

Video processing applications often store a full frame of video data to process the frame and modify the next frame. In such designs video frames are stored in external memory while FPGA resources are used to process same data. This example shows how to design a video application with HDMI input and output performing histogram equalization using external memory for video frame buffering.

Open Example
Streaming Data from Hardware to Software

Streaming Data from Hardware to Software

Presents a systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC Blockset. Applications are often partitioned between hardware logic and embedded processor on a system-on-chip (SoC) device to meet throughput, latency and processing requirements. You will design and simulate the entire application comprising of FPGA & processor algorithms, memory interface and task scheduling to meet the system requirements. You will then validate the design on hardware by generating code from the model and implementing on a SoC device.

Open Example
Streaming Data from Software to Hardware

Streaming Data from Software to Hardware

Design the data-path from an embedded processor to hardware logic (FPGA) using SoC Blockset™. Design and simulate the entire application comprising of FPGA and processor algorithms, memory interface, and task scheduling to meet the system requirements. Then, validate the design on hardware by generating code from the model and implementing it on a System-on-Chip (SoC) device.

Open Example
Analyze Memory Bandwidth Using Traffic Generators

Analyze Memory Bandwidth Using Traffic Generators

Demonstrates how to analyze memory bandwidth for an SoC application. In memory-intensive hardware designs, you may have multiple masters accessing a common DDR memory. In such cases, it is important to analyze the dynamic requirement of all memory masters to guide algorithm design and hardware board requirement for deployment. You can simulate the memory traffic using Memory traffic generators, analyze the bandwidth usage and verify it on the hardware.

Open Example
Triggering Software Tasks by FPGA Interrupts

Triggering Software Tasks by FPGA Interrupts

Model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.

Open Example

SoC Blockset Documentation

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