Implement on Device

Generate code and deploy SoC applications on SoC device

SoC Blockset™ exports reference designs for ASICs, FPGAs, and systems on a chip (SoC) by using Xilinx® and Intel® design tools. Automatically generate hardware and software code, and execute on an SoC device by using the SoC Builder tool. Code generation requires HDL Coder™, Embedded Coder®, or both.

Tools

SoC BuilderBuild, load, and execute SoC model on SoC, FPGA, and MCU boards
Memory MapperConfigure memory map for SoC application
Task MappingMap tasks in the SoC to interrupt service routines on the hardware board
Peripheral ConfigurationMap peripherals in the SoC model to peripheral registers in the MCU

Functions

socExportReferenceDesignExport custom reference design for HDL Workflow Advisor

Simulink Configuration Parameters

Hardware Implementation Pane

Topics

SoC Generation Workflows

Choose between the SoC Builder tool and the exportReferenceDesign function for deploying your design on an SoC device.

Generate SoC Design

Generate an SoC design and run it on an SoC device using the SoC Builder tool.

Export Custom Reference Design from SoC Model

Use the socExportReferenceDesign function to export a custom reference design from an SoC Blockset model.

Code Generation of Software Tasks

Mapping between tasks in an SoC application model and threads in generated code.

Supported Third-Party Tools and Hardware

Version support for third-party tools.

Troubleshooting

Build Error When FPGA or Processor Model Not Detected

Unsupported mode in when generating SoC design using SoC Builder.

Related Information

Featured Examples

Streaming Data from Hardware to Software

Streaming Data from Hardware to Software

Presents a systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC Blockset. Applications are often partitioned between hardware logic and embedded processor on a system-on-chip (SoC) device to meet throughput, latency and processing requirements. You will design and simulate the entire application comprising of FPGA & processor algorithms, memory interface and task scheduling to meet the system requirements. You will then validate the design on hardware by generating code from the model and implementing on a SoC device.

Open Example
Packet-Based ADS-B Transceiver

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Open Example
Export Custom Reference Design

Export Custom Reference Design

Export a custom reference design from an SoC model by using the Soc Blockset™ socExportReferenceDesign function. After creating the custom reference design, use the HDL Workflow Advisor tool from HDL Coder™ to integrate an IP core into the reference design.

Open Example

SoC Blockset Documentation

Support