Select an ADC Read block from the model to apply the code generation parameter configurations.

Example: RefModel/ADC Read

Open the ADC Read block selected in the Simulink block parameter in the model.

Select the ADC module A through D on the hardware board.

Identify the start-of-conversion trigger by number.

Select the input channel to which this ADC conversion applies.

Define the length of the acquisition period in ADC clock cycles. The value of this parameter depends on the SYSCLK and the minimum ADC sample time.

Select the event source that triggers the start of the conversion.

At the end of conversion, use the ADCINT1 or ADCINT2 interrupt to trigger a start of conversion. This loop creates a continuous sequence of conversions. The default selection, No ADCINT disables this parameter. To set the interrupt, select the Post interrupt at EOC trigger option, and choose the appropriate interrupt.

Enable post interrupts when the ADC triggers EOC pulses. When you select this option, the dialog box displays the Interrupt selection and Interrupt continuous mode options.

Select which ADCINT# interrupt the ADC posts to after triggering an EOC pulse.

When the ADC generates an end of conversion (EOC) signal, generate an ADCINT# interrupt, whether the previous interrupt flag has been acknowledged or not.

Select an PWM Write block from the model to apply the code generation parameter configurations.

Example: RefModel/PWM Write

Open the PWM Write block selected in the Simulink block parameter in the model.

Select the appropriate ePWM module, ePWMx, where x is a positive integer.

Set the high speed time base clock prescaler divider, HSPCLKDIV.

Use the Time base clock, TBCLK, prescaler divider, CLKDIV, and the high speed time base clock, HSPCLKDIV, prescaler divider, HSPCLKDIV, to configure the Time-base clock speed, TBCLK, for the ePWM module. Calculate TBCLK using this equation: TBCLK = PWM clock/(HSPCLKDIV * CLKDIV).

For example, the default values of both CLKDIV and HSPCLKDIV are 1, and the default frequency of PWM clock is 200 MHz, so: TBCLK in Hz = 200 MHz/(1 * 1) = 200 MHz TBCLK in seconds = 1/TBCLK in Hz = 1/200 MHz = 0.005 μs.

Set the period of the ePWM counter waveform.

The timer period is in clock cycles:

The initial duty cycle of the waveform from the time the PWM peripheral starts operation until the ePWM input port receives a new value for the duty cycle is Timer period / 2.

Enables to provide a timer phase offset value.

The specified offset value is loaded in the time base counter on a synchronization event. Enter the phase offset value, TBPHS, in TBCLK cycles from 0 to 65535.

Specify the counting mode of the PWM internal counter. This figure shows three counting waveforms.

This group determines the behavior of the action qualifier (AQ) submodule. The AQ module determines which events are converted into one of the various action types, producing the required switched waveforms of the ePWMA circuit. The ePWMB always generates a complement signal of ePWMA.

This group determines the behavior of the Action Qualifier (AQ) submodule. The AQ module determines which events are converted into one of the various action types, producing the required switched waveforms of the ePWMA circuit. The ePWMB always generates a complement signal of ePWMA.

This group determines the behavior of the action qualifier (AQ) submodule. The AQ module determines which events are converted into one of the various action types, producing the required switched waveforms of the ePWMA circuit. The ePWMB always generates a complement signal of ePWMA.

This group determines the behavior of the action qualifier (AQ) submodule. The AQ module determines which events are converted into one of the various action types, producing the required switched waveforms of the ePWMA circuit. The ePWMB always generates a complement signal of ePWMA.

When shadow mode is not enabled, the CMPA register refreshes immediately. Provide different reload mode for CMPA register.

The time when the counter period resets based on the following condition:

This parameter specifies the counter match condition that triggers an ADC start of the conversion event. The choices are:

This parameter specifies the deadband delay for rising edge and falling edge in time-base clock cycles.