Test Condition

Constrain signal values in test cases

Library

Simulink Design Verifier

  • Test Condition block

Description

When operating in test generation mode, the Simulink® Design Verifier™ software produces test cases that satisfy the specified criteria (see What is Test Case Generation?). In this mode, you can use Test Condition blocks to define test conditions for signals in your model. The Values parameter lets you specify constraints on signal values during a test case simulation. The block applies the specified Values parameter to its input signal, and the Simulink Design Verifier software attempts to produce test cases that satisfy the condition.

The block's parameter dialog box also allows you to

  • Enable or disable the condition.

  • Specify that the block should display its Values parameter in the Simulink Editor.

  • Specify that the block should display its output port.

Note

The Simulink and Simulink Coder™ software ignore the Test Condition block during model simulation and code generation, respectively. The Simulink Design Verifier software uses the Test Condition block only when generating test cases for a model.

Specifying Test Conditions

Use the Values parameter to constrain signal values in test cases. Specify any combination of scalars and intervals in the form of a MATLAB® cell array. For information about cell arrays, see Cell Arrays.

Tip

If the Values parameter specifies only one scalar value, you do not need to enter it in the form of a MATLAB cell array.

Scalar values each comprise a single cell in the array, for example:

{0, 5}

A closed interval comprises a two-element vector as a cell in the array, where each element specifies an interval endpoint:

{[1, 2]}

Alternatively, you can specify scalar values using the Sldv.Point constructor, which accepts a single value as its argument. You can specify intervals using the Sldv.Interval constructor, which requires two input arguments, i.e., a lower bound and an upper bound for the interval. Optionally, you can provide one of the following values as a third input argument that specifies inclusion or exclusion of the interval endpoints:

  • '()' — Defines an open interval.

  • '[]' — Defines a closed interval.

  • '(]' — Defines a left-open interval.

  • '[)' — Defines a right-open interval.

Note

By default, Sldv.Interval considers an interval to be closed if you omit its third input argument.

As an example, the Values parameter

{0, [1, 3]}

specifies:

  • 0 — a scalar

  • [1, 3] — a closed interval

The Values parameter

{Sldv.Interval(0, 1, '[)'), Sldv.Point(1)}

specifies:

  • Sldv.Interval(0, 1, '[)') — the right-open interval [0, 1)

  • Sldv.Point(1) — a scalar

Logical Behavior of Specifications

If you specify multiple scalars and intervals for a Test Condition block, the Simulink Design Verifier software combines them using a logical OR operation when generating test cases. Consequently, the software considers the entire test condition to be satisfied if any single scalar or interval is satisfied.

Within a single scalar or interval, a test condition is generated with a logical AND operation. In this case, all signals must satisfy the constraints in order for the input to satisfy the condition.

For example, consider a two-dimensional open interval:

Sldv.Interval([-5 -5],[5 2],'()')

The zero vector [0 0] satisfies the condition because the zero elements are within the intervals -5 to 5 and -5 to 2.

The vector [0 3] does not satisfy the condition because the second element 3 falls outside the interval -5 to 2.

Data Type Support

The Test Condition block accepts signals of all built-in data types supported by the Simulink software. For a discussion on the data types supported by the Simulink software, see Data Types Supported by Simulink. The block does not support complex input signals.

Parameters

Enable

Specify whether the block is enabled. If selected (the default), Simulink Design Verifier software uses the block when generating tests for a model. Clearing this option disables the block, that is, causes the Simulink Design Verifier software to behave as if the Test Condition block did not exist. If this option is not selected, the block appears grayed out in the Simulink Editor.

Type

Specify whether the block behaves as a Test Condition or Proof Assumption block. Select Assumption to transform the Test Condition block into a Proof Assumption block.

Values

Specify the test condition (see Specifying Test Conditions).

Display values

Specify whether the block displays the contents of its Values parameter in the Simulink Editor. By default, this option is selected.

Pass through style

Specify whether the block displays an output port in the Simulink Editor. If selected (the default), the block displays its output port, allowing its input signal to pass through as the block output. If not selected, the block hides its output port and terminates the input signal. The following graphics illustrate the appearance of the block in each case.

Pass through style: Selected

Pass through style: Deselected

Introduced in R2007a