Unary Minus
Negate input
- Library:
Simulink / Math Operations
HDL Coder / HDL Floating Point Operations
HDL Coder / Math Operations
Description
The Unary Minus block negates the input.
Ports
Input
Port_1 — Signal to negate
scalar | vector | matrix | N-D array
Input signal, specified as a scalar, vector, matrix, or N-D array.
Data Types: half | single | double | int8 | int16 | int32 | int64 | fixed point
Output
Port_1 — Negation of input signal
scalar | vector | matrix | N-D array
Negation of the input signal. The output has the same data type and dimensions as the input.
Data Types: half | single | double | int8 | int16 | int32 | int64 | fixed point
Parameters
Saturate on integer overflow — Method of overflow action
off (default) | on
Select to have integer overflows saturate. Otherwise, overflows wrap.
When you select this check box, saturation applies to every internal operation on the block, not just the output, or result. In general, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.
For signed-integer data types, the unary minus of the most negative value is not representable by the data type. In this case, the Saturate on integer overflow check box controls the behavior of the block:
| Parameter Setting | Block Behavior | Examples |
|---|---|---|
Saturate on integer overflow =
on | Values saturate to the most positive value of the integer data type |
|
Saturate on integer overflow =
off | Values wrap to the most negative value of the integer data type |
|
Programmatic Use
Block Parameter:
SaturateOnIntegerOverflow |
| Type: character vector |
Values:
'off' | 'on' |
Default:
'off' |
Sample time — Specify sample time as a value other than -1
-1 (default) | scalar | vector
Specify the sample time as a value other than -1. For more information, see Specify Sample Time.
Dependencies
This parameter is not visible unless it is explicitly set to a value other than
-1. To learn more, see Blocks for Which Sample Time Is Not Recommended.
Programmatic Use
Block Parameter:
SampleTime |
| Type: character vector |
| Values: scalar or vector |
Default:
'-1' |
Block Characteristics
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
This block supports code generation for complex signals.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
This block only supports signed fixed-point data types.