Model Info

Display model properties and text in model

Library:
Simulink / Model-Wide Utilities
HDL Coder / Model-Wide Utilities

Description

The Model Info block displays model properties and text about a model on the mask of the block. Use the Model Info block dialog box to specify the content and format of the text that the block displays. You can select model properties to display on the block. In the text displayed on the block mask, Simulink^® replaces the property name with the current value of the property in the model.

Parameters

expand all

`Specify Text and Properties to Display` — Content and format of the text to display
no default

Use the Enter text and tokens to display on Model Info block edit box to specify the text and properties to display.

In the edit box, enter any text you want to display on the block mask. Edit the default text Model Info.
To display a model property on the block mask, select a property in the Model properties list and click the right arrow button.
The block adds a token of the form %<modelpropertyname> to the edit box. In the text the block mask displays, Simulink replaces the token with the value of the property.
1. For example, if you select Description in the Model properties list and click the right arrow button, then the token
```
%<Description>
```
  appears in the right edit box.
2. You could add some explanatory text before the model property, e.g. “Model description:”.
3. When you click Apply or OK, Simulink displays your new text and the current value of the model property on the block mask in the Model Editor.
See Access Model Information Programmatically for descriptions of the model properties.

If you are interested in source control information, for a flexible interface to source control tools, use a project. See Source Control in Projects.

Model Examples

Simulating Systems with Variable Transport Delay Phenomena

Two cases where you can use Simulink® to model variable transport delay phenomena.

Open Model

Block Characteristics

Data Types
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The Model Info block is ignored during code generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

When using Model Info blocks in models targeted for HDL code generation, consider using only ASCII characters in the text that you enter to display on the Model Info block. If you have non-ASCII characters in the generated HDL code, RTL simulation and synthesis tools can fail to compile the code.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

Model Info

Description

Parameters

`Specify Text and Properties to Display` — Content and format of the text to display
no default

Model Examples

Simulating Systems with Variable Transport Delay Phenomena

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

See Also

Topics

Simulink Documentation

Support

Documentation

Model Info

Description

Parameters

Specify Text and Properties to Display — Content and format of the text to display no default

Model Examples

Simulating Systems with Variable Transport Delay Phenomena

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

See Also

Topics

Simulink Documentation

Support

`Specify Text and Properties to Display` — Content and format of the text to display
no default

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.