Enabled Subsystem

Subsystem whose execution is enabled by external input

Library:
Simulink / Ports & Subsystems
HDL Coder / Ports & Subsystems

Description

The Enabled Subsystem block is a Subsystem block preconfigured as a starting point for creating a subsystem that executes when a control signal has a positive value.

Use Enabled Subsystem blocks to model:

Discontinuities
Optional functionality
Alternative functionality

Ports

Input

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`In` — Signal input to a subsystem block
scalar | vector | matrix

Placing an Inport block in a subsystem block adds an external input port to the block. The port label matches the name of the Inport block.

Use Inport blocks to get signals from the local environment.

`Enable` — Control signal input to a subsystem block
scalar | vector | matrix

Placing an Enable block in a subsystem block adds an external input port to the block and changes the block to an Enable Subsystem block.

Output

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`Out` — Signal output from a subsystem
scalar | vector | matrix

Placing an Outport block in a subsystem block adds an output port from the block. The port label on the subsystem block is the name of the Outport block.

Use Outport blocks to send signals to the local environment.

Model Examples

Enabled Subsystems

What happens when a sine wave is fed into an enabled subsystem. After running the simulation, the scope shows three plots.

Open Model

Advanced Enabled Subsystems

What happens when a sine wave is fed into an enabled subsystem. The four subsystems in the model contain integrators, either discrete or continuous as described by the Subsystem name. After running the simulation, the two scopes show the results for the discrete enabled subsystems (top scope) and continuous enabled subsystems (bottom scope.)

Open Model

Illustration of Law of Large Numbers

Use MATLAB System blocks to illustrate the law of large numbers.

Open Model

Counters Using Conditionally Executed Subsystems

The contrast between enabled subsystems and triggered subsystems for the same control signal, through the use of counter circuits. After running the simulation, the scope shows three plots.

Open Model

Merging Signals

The following Simulink® concepts:

Open Model

Building a Clutch Lock-Up Model

Use Simulink® to model and simulate a rotating clutch system. Although modeling a clutch system is difficult because of topological changes in the system dynamics during lockup, this example shows how Simulink's enabled subsystems easily handle such problems. We illustrate how to employ important Simulink modeling concepts in the creation of the clutch simulation. Designers can apply these concepts to many models with strong discontinuities and constraints that may change dynamically.

Open Model

Block Characteristics

Data Types	`Boolean^[a]` \| `bus^[a]` \| `double^[a]` \| `enumerated^[a]` \| `fixed point^[a]` \| `half^[a]` \| `integer^[a]` \| `single^[a]` \| `string^[a]`
Direct Feedthrough	`no`
Multidimensional Signals	`limited^[a]`
Variable-Size Signals	`limited^[a]`
Zero-Crossing Detection	`no`
^[a] Actual data type or capability support depends on block implementation.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual code generation support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

When using enabled subsystems in models targeted for HDL code generation, it is good practice to consider the following:

For synthesis results to match Simulink^® results, the Enable port must be driven by registered logic (with a synchronous clock) on the FPGA.
Put unit delays on Enabled Subsystem output signals. Doing so prevents the code generator from inserting extra bypass registers in the HDL code.
Enabled subsystems can affect synthesis results in the following ways:
- In some cases, the system clock speed can drop by a small percentage.
- Generated code uses more resources, scaling with the number of enabled subsystem instances and the number of output ports per subsystem.

HDL Architecture

Architecture Description

Module (default) Generate code for the subsystem and the blocks within the subsystem.

Architecture	Description
`Module` (default)	Generate code for the subsystem and the blocks within the subsystem.
`BlackBox`	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
`No HDL`	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

BlackBox

Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code.

The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.

No HDL

Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is `inherit`. See also AdaptivePipelining (HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is `inherit`. See also BalanceDelays (HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is `inherit`. See also ClockRatePipelining (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `off`. See also DistributedPipelining (HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is `none`. See also DSPStyle (HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is `inherit`. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming (HDL Coder).

Target Specification

This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.

Restrictions

HDL Coder supports HDL code generation for enabled subsystems that meet the following conditions:

The enabled subsystem is not the DUT.
The subsystem is not both triggered and enabled.
The enable signal is a scalar.
Outputs of the enabled subsystem have an initial value of 0.
All inputs and outputs of the enabled subsystem (including the enable signal) run at the same rate.
The Show output port parameter of the Enable block is set to Off.
The States when enabling parameter of the Enable block is set to held (i.e., the Enable block does not reset states when enabled).
The Output when disabled parameter for the enabled subsystem output ports is set to held (i.e., the enabled subsystem does not reset output values when disabled).
If the DUT contains the following blocks, RAMArchitecture is set to WithClockEnable:
- Dual Port RAM
- Simple Dual Port RAM
- Single Port RAM
The enabled subsystem does not contain the following blocks:
- CIC Decimation
- CIC Interpolation
- FIR Decimation
- FIR Interpolation
- Downsample
- Upsample
- HDL FIFO
- HDL Cosimulation blocks (HDL Verifier™)
- Rate Transition
- NR Polar Encoder and NR Polar Decoder (Wireless HDL Toolbox™)

Example

The Automatic Gain Controller example shows how you can use enabled subsystems in HDL code generation. To open the example, enter:

hdlcoder_agc

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type support depends on block implementation.

Documentation

Enabled Subsystem

Description