Complex to Real-Imag

Output real and imaginary parts of complex input signal

Library:
Simulink / Math Operations
HDL Coder / Math Operations

Description

The Complex to Real-Imag block outputs the real and/or imaginary part of the input signal, depending on the setting of the Output parameter. The real outputs are of the same data type as the complex input. The input can be an array (vector or matrix) of complex signals, in which case the output signals are arrays of the same dimensions. The real array contains the real parts of the corresponding complex input elements. The imaginary output similarly contains the imaginary parts of the input elements.

Ports

Input

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`Port_1` — Input signal
scalar | vector | matrix

Complex input signal that the block computes and outputs the real and/or imaginary part.

Output

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`Port_1` — Output signal
scalar | vector | matrix

Output signal that is the real and/or imaginary part of the input signal. To choose which part is output, set the Output parameter.

Parameters

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`Output` — Real and/or imaginary output specification
`Real and imag` (default) | `Real` | `Imag`

Specify if the output is the real and/or imaginary part of the input signal.

Command-Line Information

Parameter: Output

Type: character vector

Values: 'Real and imag' | 'Real' | 'Imag'

Default: 'Real and imag'

`Sample time` — Specify sample time as a value other than `-1`
`-1` (default) | scalar | vector

Specify the sample time as a value other than -1. For more information, see Specify Sample Time.

Dependencies

This parameter is not visible unless it is explicitly set to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime

Type: character vector

Values: scalar or vector

Default: '-1'

Model Examples

Variable-Size Signal Basic Operations

How variable-size signals can be generated and also illustrates some of the operations that can be applied to them. The purpose of this example is to introduce you to the basic operations associated with variable-size signals.

Open Model

Measure Frequency Response by Using Spectrum Analyzer

Emulate a spectrum analyzer that measures the frequency response of a continuous-time system driven by a complex sinusoidal signal. In this Simulink® model, the Plant block describes a second-order resonant system of the form

Block Characteristics

Data Types	`Boolean` \| `double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Documentation

Complex to Real-Imag

Description

Ports

Input

`Port_1` — Input signal
scalar | vector | matrix

Output

`Port_1` — Output signal
scalar | vector | matrix

Parameters

`Output` — Real and/or imaginary output specification
`Real and imag` (default) | `Real` | `Imag`

Command-Line Information

`Sample time` — Specify sample time as a value other than `-1`
`-1` (default) | scalar | vector

Dependencies

Programmatic Use

Model Examples

Variable-Size Signal Basic Operations

Measure Frequency Response by Using Spectrum Analyzer

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

Documentation

Complex to Real-Imag

Description

Ports

Input

Port_1 — Input signal scalar | vector | matrix

Output

Port_1 — Output signal scalar | vector | matrix

Parameters

Output — Real and/or imaginary output specification Real and imag (default) | Real | Imag

Command-Line Information

Sample time — Specify sample time as a value other than -1 -1 (default) | scalar | vector

Dependencies

Programmatic Use

Model Examples

Variable-Size Signal Basic Operations

Measure Frequency Response by Using Spectrum Analyzer

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

`Port_1` — Input signal
scalar | vector | matrix

`Port_1` — Output signal
scalar | vector | matrix

`Output` — Real and/or imaginary output specification
`Real and imag` (default) | `Real` | `Imag`

`Sample time` — Specify sample time as a value other than `-1`
`-1` (default) | scalar | vector

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.