Select elements from incoming bus
Simulink / Commonly Used Blocks
Simulink / Signal Routing
HDL Coder / Signal Routing
The Bus Selector block outputs the elements you select from the input bus. The block can output the selected elements separately or in a new virtual bus.
Port_1
— Input busInput bus, which can be virtual or nonvirtual.
For arrays of buses, you must use a Selector block to select the bus that you want to use with the Bus Selector block.
Data Types: bus
Port_1
— Selected bus elements of input busSelected bus elements of an input bus.
For each output element, this block uses a separate port from the top to the bottom of the block. If the block is rotated, see Port Location After Rotating or Flipping for the port order of various block orientations.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| string
| Boolean
| fixed point
| enumerated
| bus
Complex Number Support: Yes
Elements in the bus
— List of elements in input busList of elements in the input bus from which to select output elements.
If you change an element name while the Block Parameters dialog box is open, you can see the updated name by clicking Refresh.
To highlight the source of an element entering the block, select the element in the list and click Find.
Block Parameter:
InputSignals |
Type: cell array |
Values: element names |
Filter by name
— Search term for filtering displayed input elementsSearch term for filtering displayed input elements, specified as text. Do not enclose the search term in quotation marks. The filter does a partial string search.
To access the filtering options, click the Show filtering
options
button to the right of the Filter by
name box.
Enable regular expression
— Option to filter displayed input elements by regular expressionOption to filter the displayed input elements by regular expression.
When this parameter is enabled, entering t$
in the
Filter by name box displays all elements whose
names end with a lowercase t
(and their immediate
parents). For details, see Regular Expressions.
To access this parameter, click the Show filtering
options
button on the right side of the Filter by
name box.
Show filtered results as a flat list
— Option to display filtered results as a flat listOption to display filtered results as a flat list that uses dot notation to reflect the hierarchy of buses. By default, the filtered elements appear in a hierarchical tree.
To access this parameter, click the Show filtering
options
button on the right side of the Filter by
name box.
Selected elements
— Selected elements of input busThe selected elements of the input bus.
To specify an output element, select an element from the Elements in the bus list, and then click the Select button. The element is added at the end of the Selected elements list. To add elements below an existing element, select an element in the Selected elements list before you click Select. Elements are added below the element you selected.
If you select multiple elements from the Elements in the bus list, the order in which you select them is the order in which Simulink® inserts them in the Selected elements list.
If an output element listed in the Selected elements
list is not an input to the Bus Selector block, the element
name starts with three question marks (???
).
To change the order of the output bus elements, use the Up and Down buttons. Port connectivity with downstream blocks is maintained when you change the element order.
To remove bus elements from the block output, use the Remove button. You can select multiple contiguous elements to move or remove.
Tip
In the Simulink Editor, as you draw a new line close to the output side of a Bus Selector block when all output ports are already connected, Simulink:
Adds a port
Prompts you to specify the element to be selected
You cannot use this automatic port addition approach if:
A bus input is not connected to the Bus Selector block.
You do not specify an element in response to the prompt that appears when you draw a line close to the Bus Selector block icon.
You select the Output as virtual bus parameter.
Block Parameter:
OutputSignals |
Type: character vector |
Values: character vector in the
form of 'signal1,signal2' |
Default: none |
Output as virtual bus
— Option to output selected elements as virtual busOption to output the selected elements as a virtual bus.
By default, the block outputs each of the selected elements from a separate output port that is labeled with the corresponding bus element name. When this parameter is enabled, the block outputs the selected elements from one port, grouped in a virtual bus.
The output bus is virtual. To convert the output to a nonvirtual bus,
insert a Signal Conversion block
after the Bus Selector block. Set the Signal
Conversion block Output parameter to
Nonvirtual bus
and set the Data
type to a Simulink.Bus
object.
When the Selected elements list includes only one element and you enable Output as virtual bus, then that element is not wrapped in a bus. For example, if the element is a bus, the output element is that bus. If the element is not a bus, the output element is not a bus.
Block Parameter:
OutputAsBus |
Type: character vector |
Values:
'on' | 'off' |
Default:
'off' |
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
For buses at subsystem and model interfaces, you can use In Bus Element blocks instead of an Inport block with a Bus Selector block. In Bus Element blocks:
Reduce line complexity and clutter in a block diagram.
Make it easier to change the interface incrementally.
Allow access to a bus element closer to the point of usage, avoiding the use of a Bus Selector and Goto block configuration.
Actual data type or capability support depends on block implementation.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Bus Signals to Improve Readability of Model and Generate HDL Code (HDL Coder).
This block has a single, default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
Actual data type or capability support depends on block implementation.
Bus Assignment | Bus Creator | Bus to Vector | Out Bus Element