Assignment

Assign values to specified elements of signal

Library:
Simulink / Math Operations
HDL Coder / Math Operations

Description

The Assignment block assigns values to specified elements of the signal. You specify the indices of the elements to be assigned values either by entering the indices in the block dialog box or by connecting an external indices source or sources to the block. The signal at the block data port, U, specifies values to be assigned to Y. The block replaces the specified elements of Y with elements from the data signal.

Based on the value you enter for the Number of output dimensions parameter, a table of index options is displayed. Each row of the table corresponds to one of the output dimensions in Number of output dimensions. For each dimension, you can define the elements of the signal to work with. Specify a vector signal as a 1-D signal and a matrix signal as a 2-D signal. To enable an external index port, in the corresponding row of the table, set Index Option to Index vector (port).

For example, assume a 5-D signal with a one-based index mode. The table in the Assignment block dialog changes to include one row for each dimension. If you define each dimension with the following entries:

Row	Index Option	Index
1	`Assign all`
2	`Index vector (dialog)`	`[1 3 5]`
3	`Starting index (dialog)`	`4`
4	`Starting index (port)`
5	`Index vector (port)`

The assigned values are Y(1:end,[1 3 5],4:3+size(U,3),Idx4:Idx4+size(U,4)-1,Idx5)=U, where Idx4 and Idx5 are the input ports for dimensions 4 and 5.

When using the Assignment block in normal mode, Simulink^® initializes block outputs to zero even if the model does not explicitly initialize them. In accelerator mode, Simulink converts the model into an S-Function. This involves code generation. The code generated may not do implicit initialization of block outputs. In such cases, you must explicitly initialize the model outputs.

You can use the block to assign values to vector, matrix, or multidimensional signals.

You can use an array of buses as an input signal to an Assignment block.

Assignment Block in Conditional Subsystem

If you place an Assignment block in a conditional subsystem block, a signal buffer can be inserted in many cases, and merging of signals from Assignment blocks with partial writes can cause an error.

However, if you select the Ensure outport is virtual check box for the conditional subsystem Outport block, such cases are supported and partial writes to arrays using Assignment blocks are possible.

Ports

Input

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`Y0` — Input initialization signal
scalar | vector

The initialization signal for the output signal. If an element is not assigned another value, then the value of the output element matches this input signal value.

`U` — Input data port
scalar | vector

Value assigned to the output element when specified.

`IndxN` — `N`th index signal
scalar | vector

External port specifying an index for the assignment of the corresponding output element.

Dependencies

To enable an external index port, in the corresponding row of the Index Option table, set Index Option to Index vector (port) or Starting index (port).

Output

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`Y` — Output signal with assigned values
scalar | vector

The output signal with assigned values for the specified elements.

Parameters

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`Number of output dimensions` — Number of dimensions of the output signal
`1` (default) | integer

Enter the number of dimensions of the output signal.

Command-Line Information

Parameter: NumberOfDimensions

Type: character vector

Values: integer

Default: '1'

`Index mode` — Index mode
`One-based` (default) | `Zero-based`

Select the indexing mode. If One-based is selected, an index of 1 specifies the first element of the input vector. If Zero-based is selected, an index of 0 specifies the first element of the input vector.

Command-Line Information

Parameter: IndexMode

Type: character vector

Values: 'Zero-based' | 'One-based'

Default: 'One-based'

`Index Option` — Index method for elements
`Index vector (dialog)` (default) | `Assign all` | `Index vector (port)` | `Starting index (dialog)` | `Starting index (port)`

Define, by dimension, how the elements of the signal are to be indexed. From the list, select:

Menu Item	Action
`Assign all`	This is the default. All elements are assigned.
`Index vector (dialog)`	Enables the Index column. Enter the indices of elements.
`Index vector (port)`	Disables the Index column. The index port defines the indices of elements.
`Starting index (dialog)`	Enables the Index column. Enter the starting index of the range of elements to be assigned values.
`Starting index (port)`	Disables the Index column. The index port defines the starting index of the range of elements to be assigned values.

If you choose Index vector (port) or Starting index (port) for any dimension in the table, you can specify one of these values for the Initialize output (Y) parameter:

Initialize using input port <Y0>
Specify size for each dimension in table

Otherwise, Y0 always initializes output port Y.

The Index and Output Size columns are displayed as relevant.

Command-Line Information

Parameter: IndexOptionArray

Type: character vector

Values: 'Assign all' |

'Index vector
                                    (dialog)'

| 'Index option (port)' | 'Starting index (dialog)' | 'Starting index (port)'

Default: 'Index vector (dialog)'

`Index` — Index of elements
`1` (default) | integer

If the Index Option is Index vector (dialog), enter the index of each element you are interested in.

If the Index Option is Starting index (dialog), enter the starting index of the range of elements to be selected. The number of elements from the starting point is determined by the size of this dimension at U.

Command-Line Information

Parameter: IndexParamArray

Type: character vector

Values: cell array

Default: '{ }'

`Output Size` — Width of the block output signal
`1` (default) | integer

Enter the width of the block output signal.

Dependencies

To enable this column, select Specify size for each dimension in table for the Initialize output (Y) parameter.

Command-Line Information

Parameter: OutputSizeArray

Type: character vector

Values: cell array

Default: '{ }'

`Initialize output (Y)` — How to initialize the output signal
`Initialize using input port <Y0>` (default) | `Specify size for each dimension in the table`

Specify how to initialize the output signal.

Initialize using input port <Y0> – Signal at the input port Y0 initializes the output.
Specify size for each dimension in table – Requires you to specify the width of the block's output signal in the Output Size parameter. If the output has unassigned elements, the value of those elements is undefined.

Dependency

Enabled when you set Index Option to Index vector (port) or Starting index (port).

Command-Line Information

Parameter: OutputInitialize

Type: character vector

Values: 'Initialize using input port <Y0>' |

'Specify size for each dimension in
                                table'

Default: 'Initialize using input port <Y0>'

`Action if any output element is not assigned` — Specify whether to produce a warning or error if you have not assigned all output elements
`Error` (default) | `Warning` | `None`

Specify whether to produce a warning or error if you have not assigned all output elements. Options include:

Error — Simulink software terminates the simulation and displays an error.
Warning — Simulink software displays a warning and continues the simulation.
None — Simulink software takes no action.

Command-Line Information

Parameter: DiagnosticForDimensions

Type: character vector

Values: 'Error' | 'Warning' | 'None'

Default: 'None'

`Sample time` — Specify sample time as a value other than `-1`
`-1` (default) | scalar | vector

Specify the sample time as a value other than -1. For more information, see Specify Sample Time.

Dependencies

This parameter is not visible unless it is explicitly set to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime

Type: character vector

Values: scalar or vector

Default: '-1'

Model Examples

Iterated Assignment with the Assignment Block

Using the Assignment block to assign values computed in a For or While Iterator loop to successive elements.

Open Model

Parallel Channel Power Allocation

A potential use of the Find block. This block outputs a variable-size signal containing the indices of the nonzero values of the input.

Open Model

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Restrictions

3-dimensional matrix inputs are not supported. You can use 1-D vectors and 2-D matrices with the block.
Variable-size signals are not supported for code generation.

Documentation

Assignment

Description

Assignment Block in Conditional Subsystem

Ports

Input

Y0 — Input initialization signal scalar | vector

U — Input data port scalar | vector

IndxN — Nth index signal scalar | vector

Dependencies

Output

Y — Output signal with assigned values scalar | vector

Parameters

Number of output dimensions — Number of dimensions of the output signal 1 (default) | integer

Command-Line Information

Index mode — Index mode One-based (default) | Zero-based

Command-Line Information

Index Option — Index method for elements Index vector (dialog) (default) | Assign all | Index vector (port) | Starting index (dialog) | Starting index (port)

Command-Line Information

Index — Index of elements 1 (default) | integer

Command-Line Information

Output Size — Width of the block output signal 1 (default) | integer

Dependencies

Command-Line Information

Initialize output (Y) — How to initialize the output signal Initialize using input port <Y0> (default) | Specify size for each dimension in the table

Dependency

Command-Line Information

Action if any output element is not assigned — Specify whether to produce a warning or error if you have not assigned all output elements Error (default) | Warning | None

Command-Line Information

Sample time — Specify sample time as a value other than -1 -1 (default) | scalar | vector

Dependencies

Programmatic Use

Model Examples

Iterated Assignment with the Assignment Block

Parallel Channel Power Allocation

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

`Y0` — Input initialization signal
scalar | vector

`U` — Input data port
scalar | vector

`IndxN` — `N`th index signal
scalar | vector

`Y` — Output signal with assigned values
scalar | vector

`Number of output dimensions` — Number of dimensions of the output signal
`1` (default) | integer

`Index mode` — Index mode
`One-based` (default) | `Zero-based`

`Index Option` — Index method for elements
`Index vector (dialog)` (default) | `Assign all` | `Index vector (port)` | `Starting index (dialog)` | `Starting index (port)`

`Index` — Index of elements
`1` (default) | integer

`Output Size` — Width of the block output signal
`1` (default) | integer

`Initialize output (Y)` — How to initialize the output signal
`Initialize using input port <Y0>` (default) | `Specify size for each dimension in the table`

`Action if any output element is not assigned` — Specify whether to produce a warning or error if you have not assigned all output elements
`Error` (default) | `Warning` | `None`

`Sample time` — Specify sample time as a value other than `-1`
`-1` (default) | scalar | vector

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.