Documentation

In the Configuration Parameters dialog, on the Diagnostics > Data Validity pane, set these Data Store Memory parameters to error:

Using data store memory blocks can have significant impact on your software verification effort. Models and subsystems that use only inports and outports to pass data provide a directly traceable interface, simplifying the verification process.

To provide deterministic data transfer between different rates and tasks, use Rate Transition blocks before Data Store Write blocks or after Data Store Read blocks.

In addition to the diagnostics, you can more accurately detect data store memory access violations in your model using Simulink^® Design Verifier™. To do this, on the Design Verifier tab, select Settings. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, select Data store access violations. For more information, see Detect Data Store Access Violations in a Model (Simulink Design Verifier). A Simulink Design Verifier license is required.

Support consistent data values across different sample times or models.

Prevent unintended data corruption.

The following examples use Rate Transition blocks to provide deterministic data transfer between different rates and tasks.

For fast-to-slow transitions:

Set the rate of the slow sample time on either the Rate Transition block or the Data Store Write block.

Do not place the Rate Transition block after the Data Store Read block.

For slow-to-fast transitions:

If the Rate Transition block is after the Data Store Read block, specify the slow rate on the Data Store Read block.

If the Rate Transition block is before the Data Store Write block, use the inherited sample time for the blocks.

To support unambiguous behavior from Merge blocks,

Use Merge blocks only with conditionally executed subsystems.

Specify execution of the conditionally executed subsystems such that only one subsystem executes during a time step.

Clear block parameter Allow unequal port widths.

Simulink combines the inputs of the Merge block into a single output. The output value at any time is equal to the most recently computed output of the blocks that drive the Merge block. Therefore, the Merge block output is dependent upon the execution order of the input computations.

To provide predictable behavior of the Merge block output, you must have mutual exclusion between the conditionally executed subsystems feeding a Merge block.

Merge block parameter Allow unequal port widths is only available when configuration parameter Underspecified initialization detection is set to Classic.

hisl_0303: Configuration Parameters > Diagnostics > Merge block

hisl_0304: Configuration Parameters > Diagnostics > Model initialization

Merge block in the Simulink documentation

Consistent vector indexing method.

Supports configurable indexing:

Support only one-based indexing:

Supports only zero-based indexing:

Blocks that use a signal index include:

When using Switch blocks, avoid comparisons using the ~= operator on floating-point data types.

Due to floating-point precision issues, do not test floating-point expressions for inequality (~=).

When the model contains a Switch block computing a relational operator with the ~= operator, the inputs to the block must not be single, double, or any custom storage class that is a floating-point type. Change the data type of the input signals, or rework the model to eliminate using the ~= operator within Switch blocks.

Improve model robustness.