Import and Verify Structured Text Code

After you generate code and test benches for your subsystem, you can import them to your target IDE. Using the test bench data, you can verify that the results from your generated code match your simulation results.

If you want to import the generated code, see Generate and Automatically Import Structured Text Code.

Generate, Import, and Verify Structured Text

If you are working with the PHOENIX CONTACT (previously KW) Software MULTIPROG® 5.0/5.50 or Phoenix Contact® PC WORX™ 6.0 IDE, see Import and Verify Structured Text to PHOENIX CONTACT (previously KW) Software MULTIPROG 5.0 and Phoenix Contact PC WORX 6.0 IDEs.

Otherwise, to generate, import, and verify Structured Text code:

  1. Specify that test bench code must be generated for the subsystem.

    1. Open the PLC Coder app. Click the PLC Code tab.

    2. Click Settings.

    3. Select Generate Testbench for Subsystem.

    If you do not specify that test bench code must be generated, when you automatically verify the generated code, you see the error Testbench not selected.

  2. You can generate the code and testbench, and manually import them to your target IDE. For information on how to import generated code, see the user manual for your target IDE.

    Alternatively, after code generation, import and verify the generated code automatically. Right-click the subsystem and select PLC Code > Generate, Import, and Verify Code for Subsystem. The software:

    1. Generates the code and test bench.

    2. Starts the target IDE.

    3. Creates a project.

    4. Imports the generated code and test bench to the new project in the target IDE.

    5. Runs the generated code on the target IDE to verify it.

For information on:

Import and Verify Structured Text to PHOENIX CONTACT (previously KW) Software MULTIPROG 5.0 and Phoenix Contact PC WORX 6.0 IDEs

Before you can automatically import generated code to this IDE, create an Empty template. You must have already set your target IDE to KW-Software MULTIPROG 5.0 or Phoenix Contact PC WORX 6.0.

  1. Start the PHOENIX CONTACT (previously KW) Software MULTIPROG 5.0/5.50 or Phoenix Contact PC WORX 6.0 IDE.

  2. Select File > Delete Template. Delete any template named Empty, and click OK when done.

  3. Select File > New Project, select Project Wizard, then click OK.

    1. In the Project Name field, type Empty,

    2. In the Project Path field, type or select a path to which you have write privileges.

    3. Click Next.

    4. In the remaining wizard pages, click Next to leave the default selections. At the end of the wizard, click Finish.

    The IDE is updated with the new Empty project tree.

  4. In the project, delete everything under the following nodes:

    • Logical POUs

    • Physical Hardware

  5. Verify that the project tree has only top-level nodes for Libraries, Data Types, Logical POUs, and Physical Hardware. There must not be any subtree nodes.

  6. In the IDE, select File > Save As Template.

  7. In Template Name, type Empty.

  8. Click OK.

  9. Close the IDE interface.

Open your model, right-click the Subsystem block, and select one of the following:

  • PLC Code > Generate and Import Code for Subsystem

  • PLC Code > Generate, Import, and Verify Code for Subsystem

If you automatically generate, import, and verify code, the software:

  1. Generates the code and test bench.

  2. Starts the target IDE.

  3. Creates a project.

  4. Imports the generated code and test bench to the new project in the target IDE.

  5. Runs the generated code on the target IDE to verify it.

Troubleshooting: Long Test Bench Code Generation Time

If code generation with test bench takes too long, one possible reason is that the test bench data size exceeds the limit that Simulink® PLC Coder™ can handle. The test bench data size is directly related to the number of times the input signal is sampled during simulation. For large simulation time or more frequent sampling, the test bench data can be large.

To reduce test bench generation time, do one of the following:

  • Reduce the duration of the simulation.

  • Increase the simulation step size.

  • If you want to retain the simulation duration and the step size, divide the simulation into multiple parts. For a simulation input signal with duration [0, t], divide the input into multiple parts with durations [0, t1], [t1, t2 ], [t2, t3], etc., where t1 < t2 < t3 < .. < t. Generate test bench code for each part separately and manually import them together to your IDE.

Related Topics

Simulink PLC Coder Documentation

Support