SVPWM Generator (2-Level)

Generate pulses for SVPWM-controlled two-level converter

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Description

The SVPWM Generator (2-Level) block generates pulses for three-phase two-level DC/AC converters using the space-vector pulse width modulation (SVPWM) technique.

The converter switches are represented by the following equivalent circuit:

As shown in the following figure, the objective of the SVPWM technique is to approximate the reference voltage vector (U_ref) instantaneously by combining the switching states corresponding to the basic space vectors.

More precisely, for every PWM period, the reference vector U_ref is averaged by using its two adjacent space vectors (U₃ and U₄ in the figure) for a certain duration of time and a null vector (U₇ or U₈) for the rest of the period.

Vector	Q1	Q3	Q5
U₁	1	0	0
U₂	1	1	0
U₃	0	1	0
U₄	0	1	1
U₅	0	0	1
U₆	1	0	1
U₇	0	0	0
U₈	1	1	1

The block implements two symmetrical switching patterns[1]:

Pattern #1: With this pattern, known as Software-Determined, each PWM channel switches twice per every PWM period.

Pattern #2: With this pattern, known as Hardware-Determined, one PWM channel remains constant for the entire PWM period. Consequently, the number of switching times for this pattern is less than pattern #1. As a result, switching losses are reduced with Pattern #2.

Parameters

Data type of input reference vector (Uref)

Specify the type of reference vector.

When set to Magnitude-Angle (rad) (default), the U_ref vector is specified by the following inputs:

|U| Magnitude of Uref (value between 0 and 1)

When set to alpha-beta components, the U_ref vector is specified by the Uα and Uβ inputs.

When set to Internally generated, the U_ref is no longer an input to the block. It is internally generated in order to control the converter output voltage as specified in the output voltage parameter.

Switching pattern

When set to Pattern #1 (default), every device of the converter switches twice per every PWM period.

When set to Pattern #2, the status of one of the three arms stays constant (no switching) for the entire PWM period.

PWM frequency (Hz)

Specify the PWM frequency that determines the PWM period.

$P W M p e r i o d = 1 / P W M F r e q u e n c y$

Default is 2000.

Output voltage: [ Mag (0<m<1), Phase (degrees), Freq (Hz)]

Specify the magnitude, phase, and frequency of the output voltage of the two level converter controlled by the block. Default is [0.8 -30 50]. The magnitude of the fundamental component of the converter line-to-line output voltage is defined as

$V_{L L r m s} = m \times \frac{V_{d c}}{\sqrt{2}}$

This parameter is visible only when the Data type of input reference vector Uref parameter is set to Internally generated.

Sample time

Specify the sample time of the block, in seconds. Set to 0 to implement a continuous block. Default is 0.

Inputs and Outputs

Uref

When the Data type of input reference vector Uref parameter is set to Magnitude-Angle (rad), the two block inputs are the magnitude and the phase, in radians, of the rotating reference vector U_ref.

When the Data type of input reference vector Uref parameter is set to alpha-beta components, the two block inputs are the alpha-beta components of U_ref.

The output contains the six pulse signals to fire the self-commutated devices (Q1 to Q6) of a converter device.

Characteristics

Sample Time	Specified in the Sample Time parameter Continuous if Sample Time = 0
Scalar Expansion	No
Dimensionalized	No

Examples

The power_SVPWMGenerator2Level model uses two simple circuits to show how the SVPWM Generator (2-Level) works and to compare the two switching pattern options. Run the simulation and open the FFT Analysis tool of the Powergui block to see the harmonics and the THD value of the voltages produced by the two converters.

The model sample time is parameterized by the Ts variable set to a default value of 2e-6 s. Set Ts to 0 in the command window and change the Simulation type parameter of the Powergui block to Continuous to simulate the model in continuous mode.

References

[1] Yu, Z., Application Report SPRA524, Space-Vector PWM with TMS320C24x Using H/W & S/W Determined Switching Patterns, Texas Instruments, 1999.

Introduced in R2013a

Documentation