HDL Code Generation

Generate HDL code from Simulink models

Implement a Simulink® model or subsystem in hardware by generating HDL code and deploying that code on an Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). These examples show how to generate HDL code from Simulink models. For more information on HDL code generation from Simulink models, see HDL Code Generation from Simulink (HDL Coder).

Topics

FPGA Based Beamforming in Simulink: Part 1 - Algorithm Design

This tutorial is the first of a two-part series that will guide you through how to develop a beamformer in Simulink suitable for implementation on hardware, such as a Field Programmable Gate Array (FPGA).

FPGA Based Beamforming in Simulink: Part 2 - Code Generation

This tutorial is the second of a two-part series that will guide you through the steps to generate HDL code for a beamforming algorithm and verify that the generated code is functionally correct.

Featured Examples

Fixed-Point HDL-Optimized Minimum-Variance Distortionless-Response (MVDR) Beamformer

Fixed-Point HDL-Optimized Minimum-Variance Distortionless-Response (MVDR) Beamformer

Implement a fixed-point HDL-optimized minimum-variance distortionless-response beamformer.

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FPGA Based Monopulse Technique Workflow: Design and Code Generation

FPGA Based Monopulse Technique Workflow: Design and Code Generation

Design an FPGA implementation-ready Monopulse Technique to match a corresponding behavioral model in Simulink® using the Phased Array System Toolbox™, DSP System Toolbox™, and Fixed-Point Designer™. To verify the implementation model is functionally correct, it compares the simulation output of the implementation model with the output of the behavioral model.The term deployment here implies designing a model that is suitable for implementation on FPGA. The model is implementation ready and this will be verified in the example. The entire workflow is designed in fixed-point.

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Phased Array System Toolbox Documentation

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