Add PWM Driver Block
In the Simulink® Library Browser, add the ePWM block from Embedded Coder® Support Package for Texas Instruments™ C2000™ Processors > F2837xD.
Configure the ePWM1, ePWM2, and ePWM3 blocks for generating the PWM pulse. In the ePWM
block parameters dialog box, calculate the pulse width modulation (PWM) counter period
register value from the CPU frequency and the PWM frequency. For center-aligned PWM,
divide the value by 2.
PWM counter period = CPU clock frequency / PWM frequency / 2
See the TMS320f28379d processor ePWM peripheral for more details.
In the F2837x/07x/004x/38x ePWM block parameters dialog box, update the settings to configure PWM1 to generate PWM pulses in the target hardware as shown in this table.
| Tab and Parameter in ePWM Block | Settings |
|---|---|
General > Module | ePWM1 |
General > Timer Period | Enter the PWM period value in the CPU clock cycle
|
Counter Compare > Specify CMPA via | Input port |
Counter Compare > CMPA initial value | Enter the PWM counter period/ 2
(2500) |
Counter Compare > Specify CMPB via | Input port |
Counter Compare > CMPB initial value | Enter the PWM counter period/ 2
(2500) |
Deadband unit > Use deadband for ePWM1A | on |
Deadband unit > Use deadband for ePWM1B | on |
Deadband unit > Deadband polarity | Active high complementary (AHC) |
Deadband unit > Deadband Rising edge (RED) period (0~16383) | 15 |
Deadband unit > Deadband Falling edge (FED) period (0~16383) | 15 |
Event Trigger > Enable ADC start of conversion for module A check box (only for PWM1) | on |
Event Trigger > Start of conversion for module A event selection (only for PWM1) | Counter equals to period (CTR=PRD) |
Rename the block as ePWM1.
In the F2837x/07x/004x/38x ePWM block paramters dialog box, update the settings to configure PWM2 and PWM3 to generate PWM pulses in the target hardware. PWM2 and PWM3 are synchronized with PWM1. Follow ePWM1 configurations (other than Event Trigger) and add the configurations as shown in this table.
| Tab and Parameter in ePWM Block | Settings |
|---|---|
General > Module | ePWM2 |
General > Timer Period | Enter the PWM period value in the CPU clock cycle
|
General > Synchronization action | Set counter to phase value specified via dialog |
General > Counting direction after phase synchronization | Count up after sync |
General > Phase offset value (TBPHS) | 0 |
Counter Compare > Specify CMPA via | Input port |
Counter Compare > CMPA initial value | Enter the PWM counter period/ 2
(2500) |
Counter Compare > Specify CMPB via | Input port |
Counter Compare > CMPB initial value | Enter the PWM counter period/ 2
(2500) |
Deadband unit > Use deadband for ePWM1A | on |
Deadband unit > Use deadband for ePWM1B | on |
Deadband unit > Deadband polarity | Active high complementary (AHC) |
Deadband unit > Deadband Rising edge (RED) period (0~16383) | 15 |
Deadband unit > Deadband Falling edge (FED) period (0~16383) | 15 |
Rename the blocks as ePWM2 and ePWM3.
Select CMPA and CMPB as input ports where PWM duty is given as input. The range varies
from 0 to PWM_counter_period. PWM outputs when PWM
up-counter matches CMPA and PWM down-counter matches CMPB. By default, the system inputs
a duty cycle of 50% by selecting PWM counter period / 2.
Enable dead time in the ePWM configuration. On the Event Trigger tab of PWM1 module,
select ADC start of conversion event when the PWM counter equals the PWM period. In the
SOC Trigger tab of the ADC block, select SOCx trigger source
as ePWM1_ADCSOCA.
Synchronize the ePWM2 and ePWM3 blocks with the ePWM1 block by setting the synchronization timing to the moment when the PWM counter equals to zero in the ePWM2 and ePWM3 blocks.
The ePWM blocks expect the duty cycle value to range from 0 to
period counter register (5000). Control_System subsystem outputs the
PWM in the range -1 to 1. This model scales the
output to 0 to 5000 (period counter value).
For simulation, add a variant source/sink to the hardware driver block for simulation and code generation.
