You can generate HDL code from a model with both Simulink® and Xilinx® blocks using Xilinx System Generator (XSG) subsystems.
Using both Simulink and Xilinx blocks in your model provides the following benefits:
A single platform for combined Simulink and Xilinx System Generator simulation, code generation, and synthesis.
Targeted code generation: Xilinx System Generator for DSP generates code from Xilinx blocks; HDL Coder™ generates code from Simulink blocks.
HDL Coder area and speed optimizations for Simulink components.
You must group your Xilinx blocks into one or more Xilinx System Generator (XSG) subsystems for code generation. An XSG subsystem can contain a hierarchy of subsystems.
To generate code from a Xilinx System Generator subsystem:
Use Vivado® or ISE Design Suite 13.4 or later.
If your design uses boolean data types, select the Use STD_LOGIC type
for Boolean or 1 bit wide gateways setting on the Xilinx System Generator window. By default, Xilinx System Generator uses std_logic_vector to represent
boolean types whereas HDL Coder uses std_logic, which can result in a
mismatch.
An XSG subsystem is a Subsystem block with:
Architecture set to Module.
One System Generator token, placed at the top level of the XSG subsystem hierarchy.
Xilinx blocks.
Simulink blocks not requiring code generation.
Input and output ports connected directly to Gateway In or Gateway Out blocks.
Propagate data type to output option enabled on Gateway Out blocks.
Matching input and output data types on Gateway In blocks. See Limitations for Code Generation from Xilinx System Generator Subsystems.
Create a subsystem containing the Xilinx blocks and set its architecture to Module.
Add a System Generator token at the top level of the subsystem.
You can have subsystem hierarchy in a Xilinx System Generator subsystem, but there must be a System Generator token at the top level of the hierarchy.
Connect each subsystem input or output port directly to a Gateway In or Gateway Out block.
On each Gateway Out block, select the Propagate data type to output option.
Code generation from Xilinx System Generator (XSG) subsystems has the following limitations:
ConstrainedOutputPipeline, InputPipeline,
and OutputPipeline are the only valid block properties
for an XSG subsystem.
HDL Coder does not generate code for blocks within an XSG subsystem, including Simulink blocks.
Gateway In blocks must not do nontrivial data type
conversion. For example, a Gateway In block can convert between the sfix8_en6 and Fix_8_6 data
types, but changing data sign, word length, or fraction length is
not allowed.
For Verilog® code generation, Simulink block names in your design cannot be the same as Xilinx names. Similarly, Xilinx blocks in your design cannot have the same name as other Xilinx blocks. HDL Coder cannot resolve these name conflicts, and generates an error late in the code generation process.