These guidelines illustrate the recommended settings for modeling delays in your model. You model delays by using blocks available in the Discrete Library. Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.
2.6.1
Recommended
For blocks in your model to be inferred as a flipflop on the target FPGA, use Delay blocks. You can specify a local reset and enable signal for each Delay block.
By default, the Delay length of the block is set to
2. In this case, the input to the block passes to the
output after two time steps. If the Delay length is set to
0, the input passes to the output without
any delay. The generated HDL code treats the
block as a wire. To infer a flipflop or register on the target device, set the
Source to dialog and specify
a Delay length greater than zero.
Do not use the Unit Delay Enabled, Unit Delay Resettable, and Unit Delay Enabled Resettable blocks for HDL code generation. These blocks have been obsoleted. Instead, replace these blocks with the Unit Delay Enabled Synchronous, Unit Delay Resettable Synchronous, and Unit Delay Enabled Resettable Synchronous blocks. These blocks use the State Control block for synchronous hardware behavior. To perform this replacement in your model, run the model check Check for obsolete Unit Delay Enabled/Resettable Blocks.
2.6.2
Mandatory
When you generate HDL code for the DUT Subsystem that uses From and Goto blocks:
Do not use From and Goto blocks across the boundary of the DUT subsystem. To connect the input and output ports of the DUT, use Inport and Outport blocks instead.
Do not use From and Goto blocks across the boundary of an Atomic Subsystem. To connect the input and output ports of the DUT, use Inport and Outport blocks instead.
Scope of From and Goto blocks must
be local to a subsystem hierarchy. Set Tag
Visibility of the blocks to
local or
Scoped. HDL code generation does not
support Tag Visibility of the blocks set to
global.
Using From and Goto blocks across a subsystem
hierarchy can impact the readability of the model. Before generating HDL code,
it is recommended that you use From and Goto
blocks in the same subsystem and use local or
Scoped visibility. When you generate HDL code, in
the generated model, each Goto and From block
becomes a pair of From and Goto subsystems
connected back to back.