Delay input signal by one sample period when external Enable signal is true
HDL Coder / Discrete
The Unit Delay Enabled Synchronous block delays the input signal u by one sample period when the external Enable signal is true. When the Enable signal is false, the state and output signal hold the previous value. The Enable signal is true when E is not zero and false when E is zero.
The Unit Delay Enabled Synchronous block implementation consists of a
Synchronous Subsystem that contains an Enabled Delay
block with a Delay length of one and a State Control
block in Synchronous
mode. When you use this block in your model and
have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware
resources due to the Synchronous
behavior of the State Control block.
The block does not support vector inputs on the Enable port.
You cannot use the block inside Enabled Subsystem,
Triggered Subsystem, or Resettable Subsystem
blocks that use Classic
semantics. The Subsystem must use
Synchronous
semantics.