This example shows how to read data from the DUT ports that are
mapped to AXI4 slave interfaces.
Create an fpga
object with Xilinx
as
Vendor
.
hFPGA =
fpga with properties:
Vendor: "Xilinx"
Interfaces: [0x0 fpgaio.interface.InterfaceBase]
Add the AXI4 slave interface to the hFPGA
object by using the
addAXI4SlaveInterface
function.
Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort
object array and then map the port to the AXI4 slave interface.
Map the DUT port objects to the AXI4 slave interface and then read data by using the
readPort
function.