Real Partial-Systolic Q-less QR Decomposition with Forgetting Factor
Q-less QR decomposition for real-valued matrices with infinite number of rows
- Library:
Fixed-Point Designer / Matrices and Linear Algebra / Matrix Factorizations
Description
The Real Partial-Systolic Q-less QR Decomposition with Forgetting Factor block uses QR decomposition to compute the economy size upper-triangular R factor of the QR decomposition A = QR, without computing Q. A is an infinitely tall real-valued matrix representing streaming data.
The solution to A'Ax = B is x = R\R'\b.
Ports
Input
A(i,:) — Rows of real matrix A
vector
Rows of real matrix A, specified as a vector. A is an infinitely tall matrix of streaming data. If A uses a fixed-point data type, A must be signed and use binary-point scaling. Slope-bias representation is not supported for fixed-point data types.
Data Types: single | double | fixed point
validIn — Whether inputs are valid
Boolean scalar
Whether inputs are valid, specified as a Boolean scalar. This control signal
indicates when the data from the A(i,:) input port is valid. When
this value is 1 (true) and the value of ready
is 1 (true), the block captures the values at the
A(i,:) input port. When this value is 0
(false), the block ignores the input samples.
Data Types: Boolean
restart — Whether to clear internal states
Boolean scalar
Whether to clear internal states, specified as a Boolean scalar. When this value
is 1 (true), the block stops the current calculation and clears all
internal states. When this value is 0 (false) and the value at
validIn is 1 (true), the block begins a new
subframe.
Data Types: Boolean
Output
R — Upper-triangular matrix R
matrix
Economy size QR decomposition matrix R multiplied by the
Forgetting factor parameter, returned as a matrix.
R is an upper triangular matrix. The output at
R has the same data type as the input at
A(i,:).
Data Types: single | double | fixed point
validOut — Whether output data is valid
Boolean scalar
Whether the output data is valid, specified as a Boolean scalar. This control
signal indicates when the data at output port R is valid. When
this value is 1 (true), the block has successfully computed the
matrix R. When this value is 0 (false), the
output data is not valid.
Data Types: Boolean
ready — Whether block is ready
Boolean scalar
Whether the block is ready, returned as a Boolean scalar. This control signal
indicates when the block is ready for new input data. When this value is
1 (true) and validIn is
1 (true), the block accepts input data in the
next time step. When this value is 0 (false),
the block ignores input data in the next time step.
Data Types: Boolean
Parameters
Number of columns in matrix A — Number of columns in input matrix A
4 (default) | positive integer-valued scalar
Number of columns in input matrix A, specified as a positive integer-valued scalar.
Programmatic Use
Block Parameter:
n |
| Type: character vector |
| Values: positive integer-valued scalar |
Default:
4 |
Forgetting factor — Forgetting factor applied after each row of the matrix is factored
0.99 (default) | real positive scalar
Forgetting factor applied after each row of the matrix is factored, specified as a real positive scalar. The output is updated as each row of A is input indefinitely.
Programmatic Use
Block Parameter:
forgetting_factor |
| Type: character vector |
| Values: positive integer-valued scalar |
Default:
0.99 |
Algorithms
Choosing the Implementation Method
Partial-systolic implementations prioritize speed of computations over space constraints, while burst implementations prioritize space constraints at the expense of speed of the operations. The following table illustrates the tradeoffs between the implementations available for matrix decompositions and solving systems of linear equations.
| Implementation | Ready | Latency | Area | Sample block or example |
|---|---|---|---|---|
| Systolic | C | O(n) | O(mn2) | Implement Hardware-Efficient QR Decomposition Using CORDIC in a Systolic Array |
| Partial-Systolic | C | O(m) | O(n2) | |
| Partial-Systolic with Forgetting Factor | C | O(n) | O(n2) | Fixed-Point HDL-Optimized Minimum-Variance Distortionless-Response (MVDR) Beamformer |
| Burst | O(n) | O(mn2) | O(n) |
Where C is a constant proportional to the word length of the data, m is the number of rows in matrix A, and n is the number of columns in matrix A.
Block Timing
The following table provides details on the timing for the QR decomposition blocks.
| Block | validIn to ready (c cycles) | validIn to validOut (v cycles) |
|---|---|---|
| Real Partial-Systolic QR Decomposition | c = w + 8 | v = c(m + n - 1) |
| Complex Partial-Systolic QR Decomposition | c = 2w + 15 | v = c(m + n - 1) |
| Real Partial-Systolic Q-less QR Decomposition | c = w + 8 | v = c(m + n - 1) |
| Complex Partial-Systolic Q-less QR Decomposition | c = 2w + 15 | v = c(m + n - 1) |
| Real Partial-Systolic Q-less QR Decomposition with Forgetting Factor | c = w + 8 | v = c(2n - 1) |
| Complex Partial-Systolic Q-less QR Decomposition with Forgetting Factor | c = 2w + 15 | v = c(2n - 1) |
In the table, m represents the number of rows in matrix A, and n is the number of columns in matrix A. w represents the word length of A.
If the data type of A is fixed point, then w is the word length.
If the data type of A is double, then w is 53.
If the data type of A is single, then w is 24.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
| General | |
|---|---|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
Supports fixed-point data types only.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
A must be signed and use binary-point scaling. Slope-bias representation is not supported.
See Also
Blocks
- Complex Partial Systolic Q-less QR Decomposition with Forgetting Factor | Real Burst Q-less QR Decomposition | Real Partial Systolic QR Decomposition | Real Partial-Systolic Q-less QR Decomposition