bitsra

Bit shift right arithmetic

Syntax

c=bitsra(a,k)

Description

c=bitsra(a,k) returns the result of an arithmetic right shift by k bits on input a for fixed-point operations. For floating-point operations, it performs a multiply by 2^-k.

If the input is unsigned, bitsra shifts zeros into the positions of bits that it shifts right. If the input is signed, bitsra shifts the most significant bit (MSB) into the positions of bits that it shifts right.

bitsra ignores fimath properties such as RoundingMode and OverflowAction.

When a is a fi object, a and c have the same associated fimath and numerictype objects.

Examples

collapse all

Shift Right a Signed fi Input

Open Live Script

Create a signed fixed-point fi object with a value of –8, word length 4, and fraction length 0. Then display the binary value of the object.

a = fi(-8,1,4,0);
disp(bin(a))

Shift a right by 1 bit.

disp(bin(bitsra(a,1)))

bitsra shifts the MSB into the position of the bit that it shifts right.

Shift Right a Built-in int8 Input

Open Live Script

Use bitsra to shift an int8 input right by 2 bits.

a = int8(64);
bitsra(a,2)

ans = int8
    16

Shift Right Using a fi Shift Value

Open Live Script

Shift right a built-in int8 input using a fi shift value.

k = fi(2);
a = int8(64);
bitsra(a,k)

ans = int8
    16

Shift Right a Floating-Point Input

Open Live Script

Scale a floating-point double input by $2^{- 3}$ .

a = double(128);
bitsra(a,3)

ans = 16

Input Arguments

collapse all

`a` — Data that you want to shift
scalar | vector | matrix | multidimensional array

Data that you want to shift, specified as a scalar, vector, matrix, or multidimensional array of fi objects or built-in numeric types.

Complex Number Support: Yes

`k` — Number of bits to shift
non-negative integer-valued scalar

Number of bits to shift, specified as a non-negative integer-valued scalar fi object or built-in numeric type.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

Usage notes and limitations:

Generated code might not handle out of range shifting.

GPU Code Generation
Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

Usage notes and limitations:

Generated code might not handle out of range shifting.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Generates sra operator in VHDL^® code.

Generates >>> operator in Verilog^® code.

Documentation

bitsra

Syntax

Description

Examples

Shift Right a Signed fi Input

Shift Right a Built-in int8 Input

Shift Right Using a fi Shift Value

Shift Right a Floating-Point Input

Input Arguments

`a` — Data that you want to shift
scalar | vector | matrix | multidimensional array

`k` — Number of bits to shift
non-negative integer-valued scalar

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

GPU Code Generation
Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Fixed-Point Designer Documentation

Support

Documentation

bitsra

Syntax

Description

Examples

Shift Right a Signed fi Input

Shift Right a Built-in int8 Input

Shift Right Using a fi Shift Value

Shift Right a Floating-Point Input

Input Arguments

a — Data that you want to shift scalar | vector | matrix | multidimensional array

k — Number of bits to shift non-negative integer-valued scalar

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using MATLAB® Coder™.

GPU Code Generation Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Fixed-Point Designer Documentation

Support

`a` — Data that you want to shift
scalar | vector | matrix | multidimensional array

`k` — Number of bits to shift
non-negative integer-valued scalar

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

GPU Code Generation
Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.