Fully Parallel Systolic FIR Filter Implementation
Implement a 25-tap lowpass FIR filter by using the Discrete FIR Filter HDL Optimized block.
The model filters new data samples at every cycle.
Open the Model
Open the model. Inspect the block parameters. The Filter structure is set to Direct form systolic.
Run the Model and Inspect Results
Run the model. Observe the input and output signals in the generated plots.
From the model toolbar, open the Logic Analyzer. If the button is not displayed, expand the Review Results app gallery.
Note the pattern of the validOut signal.
Generate HDL Code
To generate HDL code from the Discrete FIR Filter HDL Optimized block, right-click the block and select Create Subsystem from Selection. Then right-click the subsystem and select HDL Code > Generate HDL Code for Subsystem.