Upsample

Resample input at higher rate by inserting zeros

Library

Signal Operations

dspsigops

Description

The Upsample block resamples each channel of the M_i-by-N input at a rate L times higher than the input sample rate by inserting L-1 zeros between consecutive samples. You specify the integer L in the Upsample factor parameter. The Sample offset parameter, D, allows you to delay the output samples by an integer number of sample periods. Doing so enables you to select any of the L possible output phases. The value you specify for the Sample offset parameter must be in the range $0 \leq D < (L - 1)$ .

You can use this block inside of triggered subsystems when you set the Rate options parameter to Enforce single-rate processing.

Frame-Based Processing

When you set the Input processing parameter to Columns as channels (frame based), the block upsamples each column of the input over time. In this mode, the block can perform either single-rate or multirate processing. You can use the Rate options parameter to specify how the block upsamples the input:

When you set the Rate options parameter to Enforce single-rate processing, the input and output of the block have the same sample rate. In this mode, the block outputs a signal with a proportionally larger frame size than the input. For upsampling by a factor of L, the output frame size is L times larger than the input frame size (M_o = M_i*L), but the input and output frame rates are equal.
For an example of single-rate upsampling, see the Single-Rate Processing example.
When you set the Rate options parameter to Allow multirate processing, the block treats an M_i-by-N matrix input as N independent channels. The block upsamples each column of the input over time by keeping the frame size constant (M_i=M_o), and making the output frame period (T_fo) L times shorter than the input frame period (T_fo = T_fi/L).
See the Multirate, Frame-Based Processing example to see the Upsample block in this mode.

Sample-Based Processing

When you set the Input processing parameter to Elements as channels (sample based), the block treats an M-by-N matrix input as M*N independent channels, and upsamples each channel over time. In this mode, the block always performs multirate processing. The output sample rate is L times higher than the input sample rate (T_so = T_si/L), and the input and output sizes are identical.

Zero Latency

The Upsample block has zero-tasking latency for all single-rate operations. The block is in a single-rate mode if you set the Upsample factor parameter to 1 or if you set the Input processing parameter to Columns as channels (frame based) and the Rate options parameter to Enforce single-rate processing.

The Upsample block also has zero-tasking latency for multirate operations if you run your model in Simulink^® single-tasking mode.

Zero-tasking latency means that the block propagates the first input (received at t=0) immediately following the D consecutive zeros specified by the Sample offset parameter. This output (D+1) is followed in turn by the L-1 inserted zeros and the next input sample.

Nonzero Latency

The Upsample block has tasking latency for multirate, multitasking operation:

In multirate, sample-based processing mode, the initial condition for each channel appears as output sample D+1, and is followed by L-1 inserted zeros. The channel's first input appears as output sample D+L+1. The Initial conditions parameter can be an M_i-by-N matrix containing one value for each channel, or a scalar to be applied to all signal channels.
In multirate, frame-based processing mode, the first row of the initial condition matrix appears as output sample D+1, and is followed by L-1 inserted rows of zeros, the second row of the initial condition matrix, and so on. The first row of the first input matrix appears in the output as sample M_iL+D+1. The Initial conditions parameter can be an M_i-by-N matrix, or a scalar to be repeated across all elements of the input matrix.

Note

For more information on latency and the Simulink tasking modes, see Excess Algorithmic Delay (Tasking Latency) and Time-Based Scheduling and Code Generation (Simulink Coder).

Examples

Example 3. Example: Single-Rate Processing

In the ex_upsample_ref2 model, the Upsample block resamples a single-channel input with a frame size of 16. The block upsamples the input by a factor of 4. Thus, the output of the block has a frame size of 64. Because the block is in single-rate processing mode, the input and output frame rates are identical.

Example 4. Example: Multirate, Frame-Based Processing

In the ex_upsample_ref1 model, the Upsample block resamples a single-channel input with a frame period of 1 second. The block upsamples the input by a factor of 4. Thus, the output of the block has a frame period of 0.25 seconds. Because the block is in multirate processing mode, the input and output frame sizes are identical.

Parameters

Upsample factor

The integer factor, L, by which to increase the input sample rate.

Sample offset

The sample offset, D, which must be an integer in the range [0,L-1].

Input processing

Specify how the block should process the input. You can set this parameter to one of the following options:

Columns as channels (frame based) — When you select this option, the block treats each column of the input as a separate channel. In this mode, the block can perform single-rate or multirate processing.
Elements as channels (sample based) — When you select this option, the block treats each element of the input as a separate channel. In this mode, the block always performs multirate processing.

Rate options

Specify the method by which the block upsamples the input. You can select one of the following options:

Enforce single-rate processing — When you select this option, the block maintains the input sample rate by increasing the output frame size by a factor of L. To select this option, you must set the Input processing parameter to Columns as channels (frame based).
Allow multirate processing — When you select this option, the block resamples the signal such that the output sample rate is L times faster than the input sample rate.

Initial conditions

The value with which the block is initialized for cases of nonzero latency, a scalar or matrix. This value appears in the output as sample D+1. This parameter appears only when you configure the block to perform multirate processing.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers
Output	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

Consider whether your model can use the Repeat block instead of the Upsample block. The Repeat block uses fewer hardware resources, so it is a best practice to use Upsample only when your algorithm requires zero-padding upsampling.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

Input processing set to Columns as channels (frame based) is not supported.

Complex Data Support

This block supports code generation for complex signals.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a

Downsample	DSP System Toolbox
FIR Interpolation	DSP System Toolbox
FIR Rate Conversion	DSP System Toolbox
Repeat	DSP System Toolbox

Documentation

Upsample

Library

Description

Frame-Based Processing

Sample-Based Processing

Zero Latency

Nonzero Latency

Examples

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

Documentation

Upsample

Library

Description

Frame-Based Processing

Sample-Based Processing

Zero Latency

Nonzero Latency

Examples

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.