Multiport Selector

Distribute arbitrary subsets of input rows or columns to multiple output ports

Library

Signal Management / Indexing

dspindex

Description

The Multiport Selector block extracts multiple subsets of rows or columns from M-by-N input matrix u, and propagates each new submatrix to a distinct output port. The block treats an unoriented length-M vector input as an M-by-1 matrix.

The Indices to output parameter is a cell array whose kth cell contains a one-dimensional indexing expression specifying the subset of input rows or columns to be propagated to the kth output port. The total number of cells in the array determines the number of output ports on the block.

When you set the Select parameter to Rows, the block uses the one-dimensional indices you specify to select matrix rows, and all elements on the chosen rows are included. When you set the Select parameter to Columns, the block uses the one-dimensional indices you specify to select matrix columns, and all elements on the chosen columns are included. A given input row or column can appear any number of times in any of the outputs, or not at all.

When an index references a nonexistent row or column of the input, the block reacts with the action you specify using the Invalid index parameter.

Examples

Example 1

Consider the following Indices to output cell array:

{4,[1:2 5],[7;8],10:-1:6}

This is a four-cell array, which requires the block to generate four independent outputs (each at a distinct port). The table below shows the dimensions of these outputs when Select = Rows and the input dimension is M-by-N.

Cell	Expression	Description	Output Size
1	`4`	Row 4 of input	1-by-N
2	`[1:2 5]`	Rows 1, 2, and 5 of input	3-by-N
3	`[7;8]`	Rows 7 and 8 of input	2-by-N
4	`10:-1:6`	Rows 10, 9, 8, 7, and 6 of input	5-by-N

Parameters

Select

Specify the dimension of the input to select, Rows or Columns.

Indices to output

A cell array specifying the row- or column-subsets to propagate to each of the output ports. The number of cells in the array determines the number of output ports on the block.

Invalid index

Specify how the block handles an invalid index value. You can select one of the following options:

Clip index — Clip the index to the nearest valid value, and do not issue an alert.
For example, if the block receives a 64-by-4 input and the Select parameter is set to Rows, the block clips an index of 72 to 64. For the same input, if the Select parameter is set to Columns, the block clips an index of 72 to 4. In both cases, the block clips an index of -2 to 1.
Clip and warn — Clip the index to the nearest valid value and display a warning message at the MATLAB^® command line.
Generate error — Display an error dialog box and terminate the simulation.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers Enumerated
Outputs	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers Enumerated

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a

Permute Matrix	DSP System Toolbox
Selector (Simulink)	Simulink
Submatrix	DSP System Toolbox
Variable Selector	DSP System Toolbox

Documentation

Multiport Selector

Library

Description

Examples

Example 1

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

Documentation

Multiport Selector

Library

Description

Examples

Example 1

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.