Convert 1-D to 2-D

Reshape 1-D or 2-D input to 2-D matrix with specified dimensions

Library

Signal Management / Signal Attributes

dspsigattribs

Description

The Convert 1-D to 2-D block reshapes a length-M_i 1-D vector or an M_i-by-N_i matrix to an M_o-by-N_o matrix, where M_o is specified by the Number of output rows parameter, and N_o is specified by the Number of output columns parameter.

y = reshape(u,Mo,No)							% Equivalent MATLAB code

The input is reshaped columnwise, as shown in the two cases below. The length-6 vector and the 2-by-3 matrix are both reshaped to the same 3-by-2 output matrix.

An error is generated when (M_o*N_o)≠(M_i*N_i). That is, the total number of input elements must be conserved in the output.

The output is frame based when you select the Frame-based output check box; otherwise, the output is sample based.

Parameters

Number of output rows: The number of rows, M_o, in the output matrix.
Number of output columns: The number of rows, N_o, in the output matrix.
Frame-based output: Creates a frame-based output when selected.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers
Output	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a pass-through implementation.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a

Buffer	DSP System Toolbox
Convert 2-D to 1-D	DSP System Toolbox
Frame Conversion	DSP System Toolbox
Reshape (Simulink)	Simulink
Submatrix	DSP System Toolbox

Documentation

Convert 1-D to 2-D

Library

Description

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

Documentation

Convert 1-D to 2-D

Library

Description

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.