Package: dlhdl
Configure custom deep learning processor
Use the dlhdl.ProcessorConfig
class to configure a custom processor,
which is then passed on to the dlhdl.buildProcessor
class to generate a
custom deep learning processor.
The dlhdl.ProcessorConfig
class creates a custom processor configuration
object that you can use to specify the processor parameters. The processor parameters are then
used by the dlhdl.buildProcessor
class to build and generate code for your
custom deep learning processor.
ProcessorConfig
ObjecthPC = dlhdl.ProcessorConfig hPC = Processing Module "conv" ConvThreadNumber: 16 InputMemorySize: [227 227 3] OutputMemorySize: [227 227 3] FeatureSizeLimit: 1024 Processing Module "fc" FCThreadNumber: 4 InputMemorySize: 25088 OutputMemorySize: 4096 System Level Properties TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit' TargetFrequency: 200 SynthesisTool: 'Xilinx Vivado' ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM' SynthesisToolChipFamily: 'Zynq UltraScale+' SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e' SynthesisToolPackageName: '' SynthesisToolSpeedValue: ''
ProcessorConfig
ObjecthPC.TargetPlatform = 'Xilinx Zynq ZC706 evaluation kit'; >> hPC.SynthesisTool = 'Xilinx Vivado'; >> hPC.TargetFrequency = 180;
The result of the properties modification is:
hPC hPC = Processing Module "conv" ConvThreadNumber: 16 InputMemorySize: [227 227 3] OutputMemorySize: [227 227 3] FeatureSizeLimit: 1024 Processing Module "fc" FCThreadNumber: 4 InputMemorySize: 25088 OutputMemorySize: 4096 System Level Properties TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit' TargetFrequency: 180 SynthesisTool: 'Xilinx Vivado' ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM' SynthesisToolChipFamily: 'Zynq UltraScale+' SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e' SynthesisToolPackageName: '' SynthesisToolSpeedValue: ''