plcgenerateladder
(Has been removed) Generate Ladder Diagram code from Stateflow chart
plcgenerateladder will be removed in a future release. For more information, see Compatibility Considerations.
Description
plcgenerateladder( generates code from a Stateflow® chart that you can import to an IDE such as CODESYS 3.5 and view as a ladder diagram.chartPath)
plcgenerateladder( uses additional options specified by one or more chartPath,Name,Value)Name,Value pair arguments. For instance, you can create a validation model or test bench to compare the generated Ladder Diagram code against the original Stateflow chart.
Input Arguments
chartPath — Full path name of the Stateflow chart
character vector
Full path name of the Stateflow chart relative to the top level Simulink® model, specified as a character vector. To obtain the full path, select the Stateflow chart in your model and use the gcb function.
The Stateflow chart must have these properties:
The inputs and outputs to the chart must be Boolean. These inputs and outputs correspond to the input and output terminals of your PLC.
Each state of the chart must correspond to a chart output.
The expressions controlling the transition between states must involve only Boolean operations between the inputs.
For instance, in the following chart, c1, c2, c3, and c4 are Boolean inputs to the model. A1, A2, A3, and A4 are Boolean outputs from the model.
Some advanced Stateflow features are not supported because of inherent restrictions in ladder logic semantics. See the full list of unsupported features.
Example: gcb, 'ThreeAspectAutoSignal/Subsystem/AutoSignalChart'
Name-Value Pair Arguments
Specify optional
comma-separated pairs of Name,Value arguments. Name is
the argument name and Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
Name1,Value1,...,NameN,ValueN.
'GenerateTestBench','on','PLC_OutputDir','laddereqn' generates test bench code in addition to the ladder diagram and places the generated files in the subfolder laddereqn of the current working folder.'GenerateTestBench' — Generate test bench for validation
'off' (default) | 'on'
Specify whether a test bench must be generated.
You can import the Ladder Diagram code and the test bench together to a target IDE such as CODESYS 3.5. In the IDE, you can validate the ladder diagram against the test bench.
'InsertGuardResets' — Add reset coils to safeguard against multiple active states
'off' (default) | 'on'
In the ladder diagram, when the output coil corresponding to the active state is turned on, reset coils can be used to force deactivation of other states. The reset coils act as a safeguard against multiple states being simultaneously active. Specify whether the reset coils must be generated.
If you do not enable this option, each output is a coil that represents a state in the chart.
The following figure shows an output of the diagram when imported into the CODESYS 3.5 IDE. The output coil represents a state
A1in the chart. When the state is active, the coil receives power.
If you enable this option, each output is a coil that represents a state of the chart. The output is also coupled with reset coils that represent the other states. When a particular state is active, the reset coils force deactivation of the other states.
The following figure shows an output in the ladder diagram when viewed in the CODESYS 3.5 IDE. The output coil represents a state
A1. To avoid multiple states from being simultaneously active, the signal that turns the coil on also turns on the reset coils associated with the other statesA2,A3, andA4.
'GenerateValidationModel' — Generate model with Ladder Diagram code for validation
'off' (default) | 'on'
Specify whether a validation model must be generated. You can use the validation model to compare the generated Ladder Diagram code against the original Stateflow chart.
The validation model has two Subsystem blocks:
The first block has the original Stateflow Chart.
The second block has the Ladder Diagram code in a MATLAB Function block.
When you simulate this validation model, for all inputs, the software verifies the output of the second block against the first block. If the output of the second Subsystem block does not match the first, the simulation fails.
'PLC_OutputDir' — Path relative to current folder where generated files are placed
'plcsrc' (default) | character vector
Path relative to the current folder, specified as a character vector. The generated code files are placed in this subfolder. If you do not specify a value, the subfolder plcsrc is used.
The output folder must not have the same name as the current folder. For instance, if you do not specify an output folder, plcsrc is used. If the current folder is also plcsrc, an error occurs.
Example: 'out\plccode'