Xilinx Zynq Platform
HDL Coder™ can generate an IP core, integrate it into your EDK project, and program the Zynq hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM® processor. See Hardware-Software Co-Design Workflow for SoC Platforms.
To deploy your design to the Zynq hardware, you must install the HDL Coder Support Package for Xilinx Zynq Platform. For installation information, see HDL Coder Supported Hardware.
Classes
hdlcoder.Board | Board registration object that describes SoC custom board |
hdlcoder.ReferenceDesign | Reference design registration object that describes SoC reference design |
hdlcoder.WorkflowConfig | Configure HDL code generation and deployment workflows |
Topics
Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar or vector ports and read back values.
Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware
Debug IP Core Using FPGA Data Capture
This example shows how to debug HDL Coder generated IP Core using HDL Verifier's FPGA Data Capture feature.
Related Information
Troubleshooting
Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
