Complex to Magnitude-Angle HDL Optimized

Compute magnitude and/or phase angle of complex signal—optimized for HDL code generation using the CORDIC algorithm

Library

DSP System Toolbox HDL Support > Math Functions

dsphdlmathfun

Description

The Complex to Magnitude-Angle HDL Optimized block computes the magnitude and/or phase angle of a complex signal. It provides hardware-friendly control signals. The block uses a pipelined Coordinate Rotation Digital Computer (CORDIC) algorithm to achieve an efficient HDL implementation.

You can also use this block to implement the atan2 function in hardware.

Signal Attributes

Port	Direction	Description	Data Type
`dataIn`	Input	Complex scalar input signal.	`fixdt()` `int32/16/8` `uint32/16/8` `double/single` are allowed for simulation but not for HDL code generation.
`validIn`	Input	Indicates that the input signal is valid. When `validIn` is high, the block captures the `dataIn` value.	`boolean`
`magnitude`	Output	Scalar output signal.	Same as `dataIn`
`angle`	Output	Scalar output signal. Optional.	Same as `dataIn`
`validOut`	Output	Indicates that the output signal is valid. When the `magnitude` or `angle` output is ready, the block sets `validOut` high .	`boolean`

Parameters

Number of iterations source

Specifies the source of Number of iterations for the CORDIC algorithm. Select Auto to set the number of iterations to the input word length − 1. If the input is double or single, Auto sets the number of iterations to 16. Select Property to set the number of iterations from Number of iterations. The default is Auto.

Number of iterations

Specifies the number of CORDIC iterations the block executes. This parameter is visible only when Number of iterations source is set to Property. The number of iterations must be less than or equal to the input data word length − 1.

The latency of the block depends on the number of iterations performed. See Latency.

Output format

Specifies which output ports are active. You can select Magnitude, Angle, or Magnitude and angle. The default is Magnitude and angle.

Angle format

Specifies the format of the angle output. You can select Normalized or Radians. Select Normalized to return output in a fixed-point format that normalizes the angles in the range [–1,1]. For more information see Normalized Angle Format. Select Radians to return output as a fixed-point value between π and −π. The default format is Normalized.

When using this block to implement the atan2 function, set this parameter to Radians.

Scale output

Scales output by the inverse of the CORDIC gain factor. The default value is selected.

Note

If you turn off output scaling, and apply the CORDIC gain elsewhere in your design, you must exclude the π/4 term. The quadrant mapping algorithm replaces the first CORDIC iteration by mapping inputs onto the angle range [0,π/4]. Therefore, the initial rotation does not contribute a gain term.

Troubleshooting

If the input is 0+0i, the output angle is undefined. The block does not implement correction logic to force the output to 0. You can ignore this output angle.

Examples

expand all

Implement atan2 Function for HDL

This example uses:

Open Model

This example shows how to use the Complex to Magnitude Angle block to implement the atan2 function in hardware. The block uses a CORDIC architecture.

The example model compares the Complex to Magnitude Angle block with the atan2 function. The Complex to Magnitude Angle block is configured to return the angle in Radians, and to not return the magnitude. The atan2 function is using the CORDIC approximation.

The Complex to Magnitude Angle block models the latency of the hardware implementation. To align the data for comparison, the reference data path includes a delay block with the same latency.

You can generate HDL from the Complex to Magnitude Angle block, if you add it to a subsystem.

Algorithm

CORDIC Algorithm

The CORDIC algorithm is a hardware-friendly method for performing trigonometric functions. It is an iterative algorithm that approximates the solution by converging toward the ideal point. The block uses CORDIC vectoring mode to iteratively rotate the input onto the real axis.

The Givens method for rotating a complex number x+iy by an angle θ is as follows. The direction of rotation, d, is +1 for counterclockwise and −1 for clockwise.

$\begin{array}{l} x_{r} = x \cos θ - d y \sin θ \\ y_{r} = y \cos θ + d x \sin θ \end{array}$

For a hardware implementation, factor out the cosθ to leave a tanθ term.

$\begin{array}{l} x_{r} = \cos θ (x - d y \tan θ) \\ y_{r} = \cos θ (y + d x \tan θ) \end{array}$

To rotate the vector onto the real axis, choose a series of rotations of θ_n so that $\tan θ_{n} = 2^{- n}$ . Remove the cosθ term so each iterative rotation uses only shift and add operations.

$\begin{array}{l} R x_{n} = x_{n - 1} - d_{n} y_{n - 1} 2^{- n} \\ R y_{n} = y_{n - 1} + d_{n} x_{n - 1} 2^{- n} \end{array}$

Combine the missing cosθ terms from each iteration into a constant, and apply it with a single multiplier to the result of the final rotation. The output magnitude is the scaled final value of x. The output angle, z, is the sum of the rotation angles.

$\begin{array}{l} x_{r} = (\cos θ_{0} \cos θ_{1} ... \cos θ_{n}) R x_{N} \\ z = \sum_{0}^{N} d_{n} θ_{n} \end{array}$

Modified CORDIC Algorithm

The convergence region for the standard CORDIC rotation is ≈±99.7°. To work around this limitation, before doing any rotation, the block maps the input into the [0,π/4] range using the following algorithm.

if abs(x) > abs(y) 
  input_mapped = [abs(x), abs(y)];
else
  input_mapped = [abs(y), abs(x)];
end

At each iteration, the block rotates the vector towards the real axis. The rotation is counterclockwise when y is negative, and clockwise when y is positive.

Quadrant mapping saves hardware resources and reduces latency by reducing the number of CORDIC pipeline stages by one. The CORDIC gain factor, Kn, therefore does not include the n=0, or cos(π/4) term.

$K_{n} = c o s θ_{1} ... \cos θ_{n} = cos (26.565) \cdot cos (14.036) \cdot cos (7.125) \cdot cos (3.576)$

After the CORDIC iterations are complete, the block corrects the angle back to its original location. First it adjusts the angle to the correct side of π/4.

if abs(x) > abs(y)
  angle_unmapped = CORDIC_out;
else
  angle_unmapped = (pi/2) - CORDIC_out;
end

Then it flips the angle to the original quadrant.

if (x < 0) 
  if (y < 0)
    output_angle = - pi + angle_unmapped;
  else
    output_angle = pi - angle_unmapped;
else
  if (y<0)
    output_angle = -angle_unmapped;

Architecture

The block generates a pipelined HDL architecture to maximize throughput. Each CORDIC iteration is done in one pipeline stage. The gain multiplier, if enabled, is implemented with Canonical Signed Digit (CSD) logic.

Input Word Length	Output Magnitude Word Length
fixdt(0,WL,FL)	fixdt(0,WL+2,FL)
fixdt(1,WL,FL)	fixdt(1,WL+1,FL)

Input Word Length	Output Angle Word Length
fixdt([ ],WL,FL)	Radians	fixdt(1,WL+3,WL)
fixdt([ ],WL,FL)	Normalized	fixdt(1,WL+3,WL+2)

The CORDIC logic at each pipeline stage implements one iteration. For each pipeline stage, the shift and angle rotation are constants.

When you set Output format to Magnitude, the block does not generate HDL code for the angle accumulation and quadrant correction logic.

Normalized Angle Format

This format normalizes the fixed-point radian angle values around the unit circle. This is a more efficient use of bits than a range of [0,2π] radians. Normalized angle format also enables wraparound at 0/2π without additional detect and correct logic.

For example, representing the angle with 3 bits results in the following normalized values.

Using the mapping described in Modified CORDIC Algorithm, the block normalizes the angles across [0,π/4] and maps them to the correct octant at the end of the calculation.

Latency

The output is valid Number of iterations + 4 cycles after valid input.

When you set Number of iterations source to Property, the block shows the latency immediately. When you set Number of iterations source to Auto, the block calculates the latency based on the input port data type, and displays it when you update the model.

When you set Number of iterations source to Auto, the number of iterations is input word length − 1, and the latency is input word length + 3. If the input is double or single type, the number of iterations is 16, and the latency is 20.

Performance

Performance was measured for the default configuration, with output scaling disabled and fixdt(1,16,12) input. When the generated HDL code is synthesized into a Xilinx^® Virtex^®-6 (XC6VLX240T-1FFG1156) FPGA, the design achieves 260 MHz clock frequency. It uses the following resources.

Resource	Number Used
LUT	882
FFS	792
Xilinx LogiCORE^® DSP48	0
Block RAM (16K)	0

Performance of the synthesized HDL code varies depending on your target and synthesis options.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Documentation

Complex to Magnitude-Angle HDL Optimized

Library

Description

Signal Attributes

Parameters

Note

Troubleshooting

Examples

Implement atan2 Function for HDL

Algorithm

CORDIC Algorithm

Modified CORDIC Algorithm

Architecture

Normalized Angle Format

Latency

Performance

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Complex Data Support

See Also

Topics

Introduced in R2014b

DSP System Toolbox Documentation

Support

Documentation

Complex to Magnitude-Angle HDL Optimized

Library

Description

Signal Attributes

Parameters

Note

Troubleshooting

Examples

Implement atan2 Function for HDL

Algorithm

CORDIC Algorithm

Modified CORDIC Algorithm

Architecture

Normalized Angle Format

Latency

Performance

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Complex Data Support

See Also

Topics

Introduced in R2014b

DSP System Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.