Video Stream Connector

Connect two IPs with video streaming interfaces

Library:
SoC Blockset / Hardware Logic Connectivity

Description

The Stream Connector block connects two IPs with video streaming interfaces. Use this block in the FPGA model of an SoC application to connect two IPs.

Ports

Input

expand all

`wrData` — Input video data
scalar

Input video data from the data source. Specify this value as a scalar.

`wrCtrlIn` — Input control signals accompanying pixel stream
`pixelControl` bus

Control signals accompanying the pixel stream, specified as a pixelcontrol bus containing five signals. The signals describe the validity of the pixel and its location in the frame. For additional information about the pixelcontrol bus type, see AXI4-Stream Video Interface.

Data Types: pixelcontrol

`rdCtrlIn` — Ready signal from downstream interface
boolean scalar

Control signal that indicates if the block can send video data to downstream interface. When this value is (true), the downstream block is ready to receive data.

Output

expand all

`rdData` — Output video data
scalar

Output video data to the downstream destination IP.

`rdCtrlOut` — Output control signals accompanying output pixel stream
`pixelcontrol` bus

Control signals accompanying the output video data, specified as a pixelcontrol bus containing five signals. The signals describe the validity of the pixel and its location in the frame.

Data Types: pixelcontrol

`wrCtrlOut` — Ready signal to the upstream interface
boolean scalar

Control signal that indicates that the block can receive stream data from upstream interface.

Data Types: Boolean

Model Examples

Histogram Equalization Using Video Frame Buffer

Video processing applications often store a full frame of video data to process the frame and modify the next frame. In such designs video frames are stored in external memory while FPGA resources are used to process same data. This example shows how to design a video application with HDMI input and output performing histogram equalization using external memory for video frame buffering.

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design.

Documentation

Video Stream Connector

Description

Ports

Input

`wrData` — Input video data
scalar

`wrCtrlIn` — Input control signals accompanying pixel stream
`pixelControl` bus

`rdCtrlIn` — Ready signal from downstream interface
boolean scalar

Output

`rdData` — Output video data
scalar

`rdCtrlOut` — Output control signals accompanying output pixel stream
`pixelcontrol` bus

`wrCtrlOut` — Ready signal to the upstream interface
boolean scalar

Model Examples

Histogram Equalization Using Video Frame Buffer

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

SoC Blockset Documentation

Support

Documentation

Video Stream Connector

Description

Ports

Input

wrData — Input video data scalar

wrCtrlIn — Input control signals accompanying pixel stream pixelControl bus

rdCtrlIn — Ready signal from downstream interface boolean scalar

Output

rdData — Output video data scalar

rdCtrlOut — Output control signals accompanying output pixel stream pixelcontrol bus

wrCtrlOut — Ready signal to the upstream interface boolean scalar

Model Examples

Histogram Equalization Using Video Frame Buffer

Extended Capabilities

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

SoC Blockset Documentation

Support

`wrData` — Input video data
scalar

`wrCtrlIn` — Input control signals accompanying pixel stream
`pixelControl` bus

`rdCtrlIn` — Ready signal from downstream interface
boolean scalar

`rdData` — Output video data
scalar

`rdCtrlOut` — Output control signals accompanying output pixel stream
`pixelcontrol` bus

`wrCtrlOut` — Ready signal to the upstream interface
boolean scalar

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.