Stream Connector

Connect two IPs with data streaming interfaces

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  • Library:

  • SoC Blockset / Hardware Logic Connectivity

  • Stream Connector block

Description

The Stream Connector block connects two IPs with data streaming interfaces. Use this block in the FPGA model of an SoC application to connect two IPs.

Ports

Input

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Input stream data from the data source. Specify this value as a scalar.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Control signal that indicates if the input data from the data source is valid. When this value is (true), the block accepts the values on the wrData port. When this value is (false), the block ignores the value on the wrData port.

Data Types: Boolean

Control signal that indicates the last beat of data from the upstream IP.

Data Types: Boolean

Control signal that indicates if the block can send stream data to the downstream interface. When this value is (true), the downstream block is ready to receive data.

Data Types: Boolean

Output

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Output stream data to the downstream destination IP.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Control signal that indicates if the output stream data is valid.

Data Types: Boolean

Control signal that indicates that the output stream data now has last beat of burst data.

Data Types: Boolean

Control signal that indicates if the block can receive stream data from the upstream interface.

Data Types: Boolean

Model Examples

Streaming Data from Hardware to Software

Streaming Data from Hardware to Software

Presents a systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC Blockset. Applications are often partitioned between hardware logic and embedded processor on a system-on-chip (SoC) device to meet throughput, latency and processing requirements. You will design and simulate the entire application comprising of FPGA & processor algorithms, memory interface and task scheduling to meet the system requirements. You will then validate the design on hardware by generating code from the model and implementing on a SoC device.

Extended Capabilities

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Introduced in R2019a

SoC Blockset Documentation

Support