Vector Concatenate, Matrix Concatenate

Concatenate input signals of same data type to create contiguous output signal

Library:
Simulink / Commonly Used Blocks
Simulink / Math Operations
Simulink / Signal Routing
HDL Coder / Math Operations
HDL Coder / Signal Routing

Description

The Concatenate block concatenates the input signals to create an output signal whose elements reside in contiguous locations in memory.

Tip

The Concatenate block is useful for creating an output signal that is nonvirtual. However, to create a vector of function calls, use a Mux block instead.

You use a Concatenate block to define an array of buses. For details about defining an array of buses, see Combine Buses into an Array of Buses.

The Concatenate block operates in either vector or multidimensional array concatenation mode, depending on the setting of its Mode parameter. In either case, the block concatenates the inputs from the top to bottom, or left to right, input ports.

Vector Mode

In vector mode, all input signals must be either vectors or row vectors (1-by-M matrices) or column vectors (M-by-1 matrices) or a combination of vectors and either row or column vectors. When all inputs are vectors, the output is a vector.

If any of the inputs are row or column vectors, the output is a row or column vector, respectively.

Multidimensional Array Mode

Multidimensional array mode accepts vectors and arrays of any size. It assumes that the trailing dimensions are all ones for input signals with lower dimensionality. For example, if the output is 4-D and the input is [2x3] (2-D), this block treats the input as [2x3x1x1]. The output is always an array. The Concatenate dimension parameter allows you to specify the output dimension along which the block concatenates its input arrays.

If you set the Concatenate dimension parameter to 2 and inputs are 2-D matrices, the block performs horizontal matrix concatenation and places the input matrices side-by-side to create the output matrix. For example, see the ex_concatenate_horizontal model:

If you set the Concatenate dimension parameter to 1 and inputs are 2-D matrices, the block performs vertical matrix concatenation and stacks the input matrices on top of each other to create the output matrix. For example, see the ex_concatenate_vertical model:

The input matrices must have compatible sizes for concatenation. Horizontal concatenation requires input matrices to have the same number of rows. Vertical concatenation requires the input matrices to have the same number of columns.

If you set the Mode parameter to Multidimensional array, the Concatenate dimension parameter to 3, and the inputs are 2-D matrices, the block performs multidimensional matrix concatenation. For example, see the ex_concatenate_multidims model:

Ports

Input

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`Port_1` — First input to concatenate
scalar | vector | matrix | N-D array

First input to concatenate, specified as a scalar, vector, matrix, or N-D array.

Dependencies

Inputs must be of the same data type.
Matrix and N-D array inputs are supported only when you set Mode to Multidimensional array.

`Port_N` — Nth input to concatenate
scalar | vector | matrix | N-D array

Nth input to concatenate, specified as a scalar, vector, matrix, or N-D array.

Dependencies

To enable this port, set Number of inputs to an integer greater than or equal to 2.
Inputs must be of the same data type.
Matrix and N-D array inputs are supported only when you set Mode to Multidimensional array.

Output

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`Port_1` — Concatenation of input signals
scalar | vector | matrix | N-D array

Concatenation of input signals, along specified dimension. Outputs have the same data type as the input.

Parameters

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`Number of inputs` — Number of input ports
`2` (default) | positive integer

Specify the number of inputs for the block as a real-valued, positive integer, less than or equal to 65536.

Programmatic Use

Block Parameter: NumInputs

Type: character vector

Values: positive integer

Default: '2'

`Mode` — Type of concatenation
`Vector` | `Multidimensional array`

Select the type of concatenation that this block performs. The default Mode of the Vector Concatenate block is Vector. The default Mode of the Matrix Concatenate block is Multidimensional array.

When you select Vector the block performs vector concatenation (see Vector Mode for details).
When you select Multidimensional array, the block performs matrix concatenation (see Multidimensional Array Mode for details).

Programmatic Use

Block Parameter: Mode

Type: character vector

Values: 'Vector' | 'Multidimensional array'

Default: 'Vector'

`Concatenate dimension` — Output dimension along which to concatenate input arrays
`1` (default) | scalar integer

Specify the output dimension along which to concatenate the input arrays.

To concatenate input arrays vertically, enter 1.
To concatenate input arrays horizontally, enter 2.
To perform multidimensional concatenation on the inputs, specify an integer greater than 2.

Dependencies

To enable this parameter, set Mode to Multidimensional array.

Programmatic Use

Block Parameter: ConcatenateDimension

Type: character vector

Values: scalar integer

Default: '1'

Model Examples

Horizontal Matrix Concatenation

Perform a horizontal matrix concatenation with the Matrix Concatenate block.

Open Model

Vertical Matrix Concatenation

Perform a vertical matrix concatenation with the Matrix Concatenate block.

Open Model

Multidimensional Matrix Concatenation

Perform multidimensional matrix concatenation with the Matrix Concatenate block.

Open Model

Modeling Arrays of Buses

Use arrays of buses to represent structured data compactly.

Open Model

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Restrictions

HDL code generation does not support matrices at the input or output ports of the block.

Documentation

Vector Concatenate, Matrix Concatenate