Rounding Function
Apply rounding function to signal
- Library:
Simulink / Math Operations
Description
The Rounding Function block rounds each element of the input signal to produce the output signal.
You select the type of rounding from the Function parameter list. The name of the selected function appears on the block.
Tip
Use the Rounding Function block when you want vector or matrix output.
Ports
Input
Port_1 — Input signal
scalar | vector | matrix
Input signal to which the rounding function is applied.
Data Types: single | double
Output
Port_1 — Output signal
scalar | vector | matrix
Output signal after the rounding function is applied to the input signal. The output signal has the same dimensions and data type as the input. Each element of the output signal is the result of applying the selected rounding function to the corresponding element of the input signal.
Data Types: single | double
Parameters
Function — Rounding function
floor (default) | ceil | round | fix
Choose the rounding function applied to the input signal.
| Rounding function | Rounds each element of the input signal |
|---|---|
floor | To the nearest integer value towards minus infinity |
ceil | To the nearest integer towards positive infinity |
round | To the nearest integer |
fix | To the nearest integer towards zero |
Programmatic Use
Block Parameter:
Operator |
| Type: character vector |
Values:
'floor' | 'ceil' |
'round' | 'fix' |
Default:
'floor' |
Sample time — Specify sample time as a value other than -1
-1 (default) | scalar | vector
Specify the sample time as a value other than -1. For more information, see Specify Sample Time.
Dependencies
This parameter is not visible unless it is explicitly set to a value other than
-1. To learn more, see Blocks for Which Sample Time Is Not Recommended.
Programmatic Use
Block Parameter:
SampleTime |
| Type: character vector |
| Values: scalar or vector |
Default:
'-1' |
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
HDL code generation for the block requires that you use single data types as inputs to the
block, and enable the native floating point mode. In the Configuration
Parameters dialog box, on the HDL Code Generation > Floating Point pane, for Library, select Native
Floating Point. To learn more about using the native
floating-point mode, see Getting Started with HDL Coder Native Floating-Point Support (HDL Coder) and Generate Target-Independent HDL Code with Native Floating-Point (HDL Coder).
This block has a single, default HDL architecture.
| General | |
|---|---|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
| Native Floating Point | |
|---|---|
| LatencyStrategy | Specify whether to map the blocks in your design to |
| NFPCustomLatency | To specify a value, set
LatencyStrategy to |
This block supports code generation for complex signals.