Documentation

Create Simulink Test Sequence

In Simulink, create a model for the device under test (DUT), and create a test bench for the model using Test Assessment (Simulink Test) or Test Sequence (Simulink Test) blocks. Use the Test Sequence Editor (Simulink Test) to create and edit test steps. In the test sequence, use verify statements to assess the simulation, as described in Test Sequence and Assessment Syntax (Simulink Test).

You can use multiple verify statements in your model. In SystemVerilog, each verify statement is mapped to an assertion and a coverage point. You can adjust coverage goals, filter specific assertions, and see verbose information for each of the verify statements.

The verify statement along with the Test Sequence block represents a temporal check in Simulink. When generating a SystemVerilog DPI component, the temporal logic is located in the generated C code. The SystemVerilog wrapper contains an immediate assertion that triggers when the verify condition is violated.

When simulating your design in Simulink, the simulation warns if the verify assessment fails.

You can view and inspect the simulation results by using the Simulation Data Inspector (Simulink). Open the Simulation Data Inspector by entering this code at the MATLAB^® command line.

Simulink.sdi.view

To view signals over time, select them in the left pane of the Simulation Data Inspector.

Generate a SystemVerilog DPI Component for a verify Statement

rtwbuild('My_verify_tst');

Run HDL Simulation with the Generated Component

Change your current folder to the dpi_tb folder, which is under the code generation folder in your HDL simulator installation. Start your HDL simulator, and run the generated script to start the simulation. The simulation output is consistent with the Simulink output.

After the simulation completes, coverage information is displayed for each verify statement. By default, an assertion is considered covered if it was tested at least once.

For additional information on running the HDL simulation, see Verify Generated Component Against Simulink Data.

Filter Verify Assessments

Each generated error or warning displays a unique name identifying its origin. That number is the Simulink identifier (SID) of that block. For example, this log shows an error that was generated by a block with SID Req_scenario_4:32:60.

# ** Error: Req_scenario_4:32:60: At step 'Check2' verify id 'Simulink:verify_sc4_off' Failed

You might have several steps in a test sequence that utilize a verify assessment or several DPI components logging warnings from a simulation. In your test model, you can filter the generated output for specific verify checks by specifying the associated SID as a plus argument on the command line and equating the SID to -1. For example, to turn off all of the output and functional coverage for SID Req_scenario_4:32:60, enter this code at the HDL command line.

vsim -classdebug -c -voptargs=+acc -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +Req_scenario_4:32:60=-1

Adjust Functional Coverage Goals

You can use verify statements to gather functional coverage during a SystemVerilog simulation. After generating SystemVerilog using the uvmbuild or rtwbuild (Simulink Coder) functions, define coverage goals for each verify statement. After a SystemVerilog simulation completes, view the results in the generated log file, or use a third party tool to extract the results. The default coverage goal is at least one passing execution of the verify assertion.

To increase the functional coverage goal for a specific verify assessment, specify the associated SID as a plus argument in the command line, and equate the SID to your coverage goal. For example, to increase the coverage goal of a verify statement with SID Req_scenario_4:32:60 from the default of one to two passing checks, enter this code at the HDL command line.

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +Req_scenario_4:32:60=2

Verbose Mode

By default, the generated DPI component outputs an error when the verify assessment is tested and fails. To see additional output generated by the verify assessment, enter the argument +VERBOSE_VERIFY at the HDL simulation command line. This argument adds this additional information:

For example, when using ModelSim^®, enter this code at the command line.

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +VERBOSE_VERIFY

Trace Generated SystemVerilog Error Back to Simulink Source

After running a SystemVerilog simulation with a generated test sequence, your log file displays warnings and errors. To identify which block originated a specific warning or error output, use the hilite_system (Simulink) function.

For example, to highlight the block that generated a warning for SID Req_scenario_4:32:60, enter this code at the MATLAB command line.

hilite_system('Req_scenario_4:32:60');

This figure highlights the verify statement and the test sequence block that created the warning.

For additional information about SIDs, see Simulink Identifiers (Simulink).