UVM Component Generation Overview

If you have a Simulink^® Coder™ license, you can generate a Universal Verification Methodology (UVM) test bench and additional components from a Simulink model. Generating UVM components enables a direct transition from your Simulink environment to a UVM framework.

HDL Verifier™ exports Simulink subsystems as generated C code inside UVM components with a direct programming interface (DPI). You can integrate these generated components into your existing UVM environment. You can also use the generated UVM test bench to test an HDL DUT by replacing the generated behavioral DUT with your detailed HDL design.

Prepare Simulink Model for UVM Component Generation

Your Simulink model must include these subsystems.

A DUT subsystem. This subsystem generates a SystemVerilog DPI (SVDPI) behavioral model of your DUT. For more information about SystemVerilog DPI Generation, see DPI Component Generation with Simulink.
A sequence subsystem. This subsystem creates stimulus and drives it to the DUT.
A scoreboard subsystem. This subsystem collects and checks the output of the DUT.
The sequence can also drive signals directly to the scoreboard, as illustrated in red in the Simulink Model Structure figure.

For details on how to create a subsystem, see Create Subsystems (Simulink).

Simulink Model Structure

Image shows a block diagram with a sequence, a DUT, and a scoreboard subsystem. An arrow connects from the sequence to the DUT, and another arrow connects from the DUT to the scoreboard.

In addition to the previous structure, you can optionally include these subsystems.

A driver subsystem
A monitor subsystem

When adding a monitor or a driver subsystem, this feature supports these configurations.

If your model includes a driver subsystem, then all signals coming out of the sequence must be connected to the driver or the scoreboard.
If your model includes a driver subsystem, then all signals coming out of the driver must be connected to the DUT.
If your model includes a monitor subsystem, then all signals coming out of the DUT must be connected to the monitor.
If your model includes a monitor subsystem, then all signals coming out of the monitor must be connected to the scoreboard.

This image shows a Simulink model that includes a driver subsystem and a monitor subsystem.

Image shows a block diagram with a sequence, a DUT, and a scoreboard subsystem. There is a driver subsystem between the sequence and the DUT, and a monitor subsystem between the DUT and the scoreboard.

Select System Target

Because UVM generation utilizes the technology for generating SystemVerilog DPI, you must first select a supporting system target file. Open the configuration parameters dialog box, and select Code Generation from the left pane. For System target file, click Browse, and then select systemverilog_dpi_grt.tlc from the list.

Alternatively, if you have the Embedded Coder^® product, you can select target systemverilog_dpi_ert.tlc. This target enables you to access additional code generation options when you select Code Generation from the left pane of the Configuration Parameters dialog box.

For an example of UVM generation ,see Generate Parameterized UVM Test Bench from Simulink.

Generated UVM Structure

Use the uvmbuild function to generate this structure of UVM components.

Top – This module instantiates a generated behavioral DUT and the test environment. The top module has clock and reset signals that propagate into the design.
DUT – a behavioral design-under-test module is generated from your Simulink DUT subsystem.
Test – This module includes the UVM environment and sequence class.
Sequence – This UVM object defines a set of transactions. The sequence object is generated from your Simulink sequence subsystem.
Environment – This module includes the agent and generated scoreboard.
Scoreboard – The UVM scoreboard is generated from your Simulink scoreboard subsystem.
Agent – The UVM agent includes a sequencer, driver, and monitor. If a direct path exists from the Simulink sequence subsystem to the Simulink scoreboard subsystem, an additional monitor, illustrated in red in the figure, is included to monitor that signal.
Sequencer – This module controls the flow of sequence transactions to the DUT.
Driver – This module is generated from your Simulink driver subsystem and transforms each transaction from the Sequence to signals that the behavioral DUT understands.
Monitor – This module is generated from your Simulink monitor subsystem and it samples the signals from the behavioral DUT and generates transactions that are sent to the UVM scoreboard.

For more information about the UVM components and structure, see UVM reference guide.

Generated Files and Folder Structure

When generating UVM components, HDL Verifier generates SystemVerilog DPI components from your DUT, sequence, and scoreboard subsystems. The artifacts of DPI generation are placed in three directories, one for each subsystem: DUT, sequence, and scoreboard. For each one of the three subsystems, a folder is created with these contents.

subsystem_build – This folder contains the generated SVDPI components for each one of the main subsystems (DUT, sequence, scoreboard, monitor or driver). The folder name is subsystem_build, where subsystem is replaced by DUT, sequence, scoreboard, monitor or driver. Each folder includes:

subsystem_dpi_pkg.sv – SystemVerilog package file with function declarations for the component
subsystem_dpi.sv – The generated SystemVerilog component
DPI component and header files with extensions .c and .h
Metadata and information files with extensions .mat, .txt, .dmr, .tmw, and .def
A makefile for compiling the components into .o and .so files

After generating three folders for the specified subsystems, a fourth folder is created for additional UVM component files and execution scripts. The folder is named top-model-name_uvmbuild/uvm_testbench, where top-model-name is the name of your top Simulink model. This folder includes several subfolders.

DPI_dut – This folder contains a copy of the SystemVerilog package, module files, and a .dll file from the dut_build folder.
scoreboard – This folder contains a copy of the SystemVerilog package and a .dll file from the scoreboard_build folder. This folder also includes the scoreboard class.
sequence – This folder contains a copy of the SystemVerilog package and a .dll file from the sequence_build folder. This folder also includes the sequence class, type definitions, and a boilerplate sequencer class.
top – This folder contains the SystemVerilog package and module files for the top Simulink model. This folder also contains scripts for HDL-simulator execution.
uvm_artifacts – This folder contains these SystemVerilog files.
- mw_dpi_types_pkg.sv – This file contains definitions of generated SystemVerilog types, such as enum and struct, exposed by UVM component interfaces. Only UVM components which use these types import this package.
- mw_DUT_trans.sv – This file contains a UVM object that defines the input transaction type for the scoreboard.
- mw_DUT_if.sv – This file defines the DUT SystemVerilog interface type. It contains DUT inputs and outputs, as well as ports for clock, reset, and clock-enable signals.
- mw_DUT_driver.sv – This file includes a pass-through UVM driver by default. When specifying a driver subsystem to the uvmbuild function, this module includes a scheduler and the API calls to the DPI component Driver_dpi_pkg.sv.
- mw_DUT_monitor_input.sv – This file includes a pass-through UVM monitor. The monitor samples signals from the driver to the scoreboard.
- mw_DUT_monitor.sv – This file includes a pass-through UVM monitor. The monitor samples signals from the DUT to the scoreboard. When specifying a monitor subsystem to the uvmbuild function, this module includes a scheduler and the API calls to the DPI-component Monitor_dpi_pkg.sv.
- mw_DUT_agent.sv – This file includes a UVM agent that instantiates sequence, driver, and monitor.
- mw_DUT_environment.sv – This file includes a UVM environment, that instantiates an agent and a scoreboard.
- mw_DUT_test.sv – This file includes a UVM test, that instantiates an environment and sequence. The test module starts the transactions by calling seq.start.

When specifying a monitor or a driver to the uvmbuild function, two additional directories are generated in the uvm_testbench directory.

driver – This folder is generated if you specified a monitor subsystem to the uvmbuild function. This folder contains a copy of the SystemVerilog package and a shared library file (dll-file or so-file) from the driver_build folder.
monitor – This folder is generated if you specified a monitor subsystem to the uvmbuild function. This folder contains a copy of the SystemVerilog package and a shared library file (dll-file or so-file) from the monitor_build folder.

Supported Simulink Data Types

Supported Simulink data types are converted to SystemVerilog data types, as shown in this table.

Generated SystemVerilog Types

MATLAB^®	SystemVerilog
MATLAB^®	Compatible C Type	Logic Vector	Bit Vector
`uint8`	`byte unsigned`	`logic [7:0]`	`bit [7:0]`
`uint16`	`shortint unsigned`	`logic [15:0]`	`bit [15:0]`
`uint32`	`int unsigned`	`logic [31:0]`	`bit [31:0]`
`uint64`	`longint unsigned`	`logic [63:0]`	`bit [63:0]`
`int8`	`byte`	`logic signed [7:0]`	`bit signed [7:0]`
`int16`	`shortint`	`logic signed [15:0]`	`bit signed [15:0]`
`int32`	`int`	`logic signed [31:0]`	`bit signed [31:0]`
`int64`	`longint`	`logic signed [63:0]`	`bit signed [63:0]`
`boolean`	`byte unsigned`	`logic [0:0]`	`bit [0:0]`
fixed-point	The port is sign extended to a built-in C type, such as `int`, `int unsigned`, `byte`, `byte unsigned`, etc.	`logic [n-1:0]` `logic signed [n-1:0]` The logic vector length (`n`) is equal to the `wordlength`. The sign is inherited from the fixed point type.	`bit [n-1:0]` `bit signed [n-1:0]` The bit vector length (`n`) is equal to the `wordlength`. The sign is inherited from the fixed point type.
`single`	`shortreal`
`double`	`real`
`complex`	You can choose between a SystemVerilog `struct` data type or flattened ports for real and imaginary parts in the SystemVerilog interface. To choose between these options, in the left pane of the Configuration Parameters dialog box, select Code Generation > SystemVerilog DPI section, and set Composite data type to `structure` or `flattened`.
vectors, matrices	arrays For example, a 4-by-2 matrix in Simulink is converted into a one-dimensional array of eight elements in SystemVerilog. The coder flattens matrices in column-major order.
nonvirtual bus	You can choose between a SystemVerilog `struct` type or flattened ports for separate component signals in the SystemVerilog interface. To choose between these options, in the left pane of the Configuration Parameters dialog box, select Code Generation > SystemVerilog DPI section, and set Composite data type to `structure` or `flattened`.
enumerated data types	`enum`

Limitations

HDL Verifier converts matrices and vectors to one-dimensional arrays in SystemVerilog. For example, a 4-by-2 matrix in Simulink is converted to a one-dimensional array of eight elements in SystemVerilog.
The uvmbuild function ignores Simulink components that are not specified as a DUT, sequence, scoreboard, driver, or monitor subsystems.
You can use feedback loops inside any of the subsystems, but not between them.
The sequence and scoreboard subsystems must operate at a single rate, and the fundamental sample times of their subsystems must be equal. For more information about sample times, see Sample Times in Systems (Simulink).
The fundamental sample times of the driver, DUT, and monitor subsystems must be equal. Their ports can be multirate, but the greatest common divisor (GCD) or fundamental sample time must be the same.
The sample time of the sequence and scoreboard subsystems must be greater than or equal to the fundamental sample time of the driver, DUT, and monitor.

External Websites

UVM Standard

Documentation